CPUs z Input and output z Supervisor mode

CPUs z. Input and output. z. Supervisor mode, exceptions, traps. z. Co-processors. © 2000 Morgan Kaufman Overheads for Computers as Components

I/O devices CPU status reg data reg © 2000 Morgan Kaufman Overheads for Computers as Components mechanism z. Usually includes some non-digital component. z. Typical digital interface to CPU:

Application: 8251 UART z. Universal asynchronous receiver transmitter (UART) : provides serial communication. z 8251 functions are integrated into standard PC interface chip. z. Allows many communication parameters to be programmed. © 2000 Morgan Kaufman Overheads for Computers as Components

Serial communication z. Characters are transmitted separately: no char start bit 0 bit 1 . . . bit n-1 stop time © 2000 Morgan Kaufman Overheads for Computers as Components

Serial communication parameters z. Baud (bit) rate. z. Number of bits per character. z. Parity/no parity. z. Even/odd parity. z. Length of stop bit (1, 1. 5, 2 bits). © 2000 Morgan Kaufman Overheads for Computers as Components

8251 CPU interface CPU status (8 bit) 8251 data (8 bit) © 2000 Morgan Kaufman Overheads for Computers as Components xmit/ rcv serial port

Programming I/O z. Two types of instructions can support I/O: yspecial-purpose I/O instructions; ymemory-mapped load/store instructions. z. Intel x 86 provides in, out instructions. Most other CPUs use memory-mapped I/O. z. I/O instructions do not preclude memorymapped I/O. © 2000 Morgan Kaufman Overheads for Computers as Components

ARM memory-mapped I/O z. Define location for device: DEV 1 EQU 0 x 1000 z. Read/write code: LDR LDR STR © 2000 Morgan Kaufman r 1, #DEV 1 ; set up device adrs r 0, [r 1] ; read DEV 1 r 0, #8 ; set up value to write r 0, [r 1] ; write value to device Overheads for Computers as Components

SHARC memory mapped I/O z. Device must be in external memory space (above 0 x 400000). z. Use DM to control access: I 0 = 0 x 400000; M 0 = 0; R 1 = DM(I 0, M 0); © 2000 Morgan Kaufman Overheads for Computers as Components

Peek and poke z. Traditional HLL interfaces: int peek(char *location) { return *location; } void poke(char *location, char newval) { (*location) = newval; } © 2000 Morgan Kaufman Overheads for Computers as Components

Busy/wait output z. Simplest way to program device. y. Use instructions to test when device is ready. current_char = mystring; while (*current_char != ‘’) { poke(OUT_CHAR, *current_char); while (peek(OUT_STATUS) != 0); current_char++; } © 2000 Morgan Kaufman Overheads for Computers as Components

Simultaneous busy/wait input and output while (TRUE) { /* read */ while (peek(IN_STATUS) == 0); achar = (char)peek(IN_DATA); /* write */ poke(OUT_DATA, achar); poke(OUT_STATUS, 1); while (peek(OUT_STATUS) != 0); } © 2000 Morgan Kaufman Overheads for Computers as Components

Interrupt I/O z. Busy/wait is very inefficient. y. CPU can’t do other work while testing device. y. Hard to do simultaneous I/O. z. Interrupts allow a device to change the flow of control in the CPU. y. Causes subroutine call to handle device. © 2000 Morgan Kaufman Overheads for Computers as Components

CPU PC IR intr request intr ack data/address © 2000 Morgan Kaufman status reg data reg Overheads for Computers as Components mechanism Interrupt interface

Interrupt behavior z. Based on subroutine call mechanism. z. Interrupt forces next instruction to be a subroutine call to a predetermined location. y. Return address is saved to resume executing foreground program. © 2000 Morgan Kaufman Overheads for Computers as Components

Interrupt physical interface z. CPU and device are connected by CPU bus. z. CPU and device handshake: ydevice asserts interrupt request; y. CPU asserts interrupt acknowledge when it can handle the interrupt. © 2000 Morgan Kaufman Overheads for Computers as Components

Example: character I/O handlers void input_handler() { achar = peek(IN_DATA); gotchar = TRUE; poke(IN_STATUS, 0); } void output_handler() { } © 2000 Morgan Kaufman Overheads for Computers as Components

Example: interrupt-driven main program main() { while (TRUE) { if (gotchar) { poke(OUT_DATA, achar); poke(OUT_STATUS, 1); gotchar = FALSE; } } } © 2000 Morgan Kaufman Overheads for Computers as Components

Example: interrupt I/O with buffers z. Queue for characters: a head tail © 2000 Morgan Kaufman tail Overheads for Computers as Components

Buffer-based input handler void input_handler() { char achar; if (full_buffer()) error = 1; else { achar = peek(IN_DATA); add_char(achar); } poke(IN_STATUS, 0); if (nchars == 1) { poke(OUT_DATA, remove_char(); poke(OUT_STATUS, 1); } } © 2000 Morgan Kaufman Overheads for Computers as Components

I/O sequence diagram : foreground : input : output : queue empty a empty b bc c © 2000 Morgan Kaufman Overheads for Computers as Components

Debugging interrupt code z. What if you forget to change registers? y. Foreground program can exhibit mysterious bugs. y. Bugs will be hard to repeat---depend on interrupt timing. © 2000 Morgan Kaufman Overheads for Computers as Components

Priorities and vectors z. Two mechanisms allow us to make interrupts more specific: y. Priorities determine what interrupt gets CPU first. y. Vectors determine what code is called for each type of interrupt. z. Mechanisms are orthogonal: most CPUs provide both. © 2000 Morgan Kaufman Overheads for Computers as Components

Prioritized interrupts device 1 device 2 interrupt acknowledge L 1 L 2. . Ln CPU © 2000 Morgan Kaufman Overheads for Computers as Components device n

Interrupt prioritization z. Masking: interrupt with priority lower than current priority is not recognized until pending interrupt is complete. z. Non-maskable interrupt (NMI): highestpriority, never masked. y. Often used for power-down. © 2000 Morgan Kaufman Overheads for Computers as Components

Example: Prioritized I/O : interrupts : foreground : A B C A A, B © 2000 Morgan Kaufman Overheads for Computers as Components : B : C

Interrupt vectors z. Allow different devices to be handled by different code. z. Interrupt vector table: Interrupt vector table head © 2000 Morgan Kaufman handler 0 handler 1 handler 2 handler 3 Overheads for Computers as Components

Interrupt vector acquisition : CPU : device receive request receive ack receive vector © 2000 Morgan Kaufman Overheads for Computers as Components

Generic interrupt mechanism continue execution N N ignore intr? Y intr priority > current priority? Y ack Y bus error Y timeout? N vector? Y call table[vector] © 2000 Morgan Kaufman Overheads for Computers as Components Assume priority selection is handled before this point.

Interrupt sequence z. CPU acknowledges request. z. Device sends vector. z. CPU calls handler. z. Software processes request. z. CPU restores state to foreground program. © 2000 Morgan Kaufman Overheads for Computers as Components

Sources of interrupt overhead z. Handler execution time. z. Interrupt mechanism overhead. z. Register save/restore. z. Pipeline-related penalties. z. Cache-related penalties. © 2000 Morgan Kaufman Overheads for Computers as Components

ARM interrupts z. ARM 7 supports two types of interrupts: y. Fast interrupt requests (FIQs). y. Interrupt requests (IRQs). z. Interrupt table starts at location 0. © 2000 Morgan Kaufman Overheads for Computers as Components

ARM interrupt procedure z. CPU actions: y. Save PC. Copy CPSR to SPSR. y. Force bits in CPSR to record interrupt. y. Force PC to vector. z. Handler responsibilities: y. Restore proper PC. y. Restore CPSR from SPSR. y. Clear interrupt disable flags. © 2000 Morgan Kaufman Overheads for Computers as Components

ARM interrupt latency z. Worst-case latency to respond to interrupt is 27 cycles: y. Two cycles to synchronize external request. y. Up to 20 cycles to complete current instruction. y. Three cycles for data abort. y. Two cycles to enter interrupt handling state. © 2000 Morgan Kaufman Overheads for Computers as Components

SHARC interrupt structure z. Interrupts are vectored and prioritized. z. Priorities are fixed: reset highest, user SW interrupt 3 lowest. z. Vectors are also fixed. Vector is offset in vector table. Table starts at 0 x 20000 in internal memory, 0 x 40000 in external memory. v

SHARC interrupt sequence Start: must be executing or IDLE/IDLE 16. 1. Output appropriate interrupt vector address. 2. Push PC value onto PC stack. 3. Set bit in interrupt latch register. 4. Set IMASKP to current nesting state.

SHARC interrupt return Initiated by RTI instruction. 1. Return to address at top of PC stack. 2. Pop PC stack. 3. Pop status stack if appropriate. 4. Clear bits in interrupt latch register and IMASKP.

SHARC interrupt performance Three stages of response: y 1 cycle: synchronization and latching; y 1 cycle: recognition; y 2 cycles: brancing to vector. Total latency: 3 cycles. Multiprocessor vector interrupts have 6 cycle latency.

Supervisor mode z. May want to provide protective barriers between programs. y. Avoid memory corruption. z. Need supervisor mode to manage the various programs. z. SHARC does not have a supervisor mode. © 2000 Morgan Kaufman Overheads for Computers as Components

ARM supervisor mode z. Use SWI instruction to enter supervisor mode, similar to subroutine: SWI CODE_1 z. Sets PC to 0 x 08. z. Argument to SWI is passed to supervisor mode code. z. Saves CPSR in SPSR. © 2000 Morgan Kaufman Overheads for Computers as Components

Exception z. Exception: internally detected error. z. Exceptions are synchronous with instructions but unpredictable. z. Build exception mechanism on top of interrupt mechanism. z. Exceptions are usually prioritized and vectorized. © 2000 Morgan Kaufman Overheads for Computers as Components

Trap z. Trap (software interrupt): an exception generated by an instruction. y. Call supervisor mode. z. ARM uses SWI instruction for traps. z. SHARC offers three levels of software interrupts. y. Called by setting bits in IRPTL register. © 2000 Morgan Kaufman Overheads for Computers as Components

Co-processor z. Co-processor: added function unit that is called by instruction. y. Floating-point units are often structured as co -processors. z. ARM allows up to 16 designer-selected coprocessors. y. Floating-point co-processor uses units 1 and 2. © 2000 Morgan Kaufman Overheads for Computers as Components