CPS 110 Page replacement Landon Cox February 21

CPS 110: Page replacement Landon Cox February 21, 2008

Dynamic address translation User process Virtual address Translator (MMU) Physical address ê Translator: just a data structure ê Tradeoffs ê Flexibility (sharing, growth, virtual memory) ê Size of translation data ê Speed of translation Physical memory

2. Segmentation Segment # Base Bound Segment 0 4000 700 Code Segment 1 0 500 Data segment Segment 2 Unused Segment 3 2000 1000 Segment # Stack segment Virtual memory Physical memory (3, fff). (3, 000) … (1, 4 ff). (1, 000) … (0, 6 ff). (0, 0) 46 ff. 4000 … 2 fff. 2000 … 4 ff. 0 (Stack) Offset (Data) (Code segment) (Stack segment) (Data segment)

Virtual addresses VA={b 31, b 30, …, b 12, b 11, …, b 1, b 0} High-order bits Low-order bits (segment number) (offset)

3. Paging ê Very similar to segmentation ê Allocate memory in fixed-size chunks ê Chunks are called pages ê Virtual addresses ê Virtual page # (e. g. upper 20 bits) ê Offset within the page (e. g. low 12 bits)

3. Paging ê Translation data is a page table Virtual page # Physical page # 0 10 1 15 2 20 3 invalid … … 1048574 Invalid 1048575 invalid

3. Paging ê Translation process if (virtual page # is invalid) { trap to kernel } else { physical page = pagetable[virtual page]. phys. Page. Num physical address is {physical page}{offset} }

Page size trade-offs ê If page size is too small ê Lots of page table entries ê Big page table ê If we use 4 -byte pages with 4 -byte PTEs ê Num PTEs = 2^30 = 1 billion ê 1 billion PTE * 4 bytes/PTE = 4 GB ê Would take up entire address space!

Page size trade-offs ê What if we use really big (1 GB) pages? ê Internal fragmentation ê Wasted space within the page ê Recall external fragmentation ê (wasted space between pages/segments)

Page size trade-offs ê Compromise between the two ê x 86 page size = 4 kb for 32 -bit processor ê Sparc page size = 8 kb ê For 4 KB pages, how big is the page table? ê 1 million page table entries ê 32 -bits (4 bytes) per page table entry 4 MB per page table

Paging pros and cons + Simple memory allocation + Can share lots of small pieces (how would two processes share a page? ) (how would two processes share an address space? ) + Easy to grow address space – Large page tables (even with large invalid section)

Comparing translation schemes ê Base and bounds ê Unit of translation = entire address space ê Segmentation ê Unit of translation = segment ê A few large variable-size segments/address space ê Paging ê Unit of translation = page ê Lots of small fixed-size pages/address space

What we want ê Efficient use of physical memory ê Little external or internal fragmentation ê Easy sharing between processes ê Space-efficient data structure ê How we’ll do this ê Modify paging scheme

Course administration Latest thread library score 70 Thread library scores 60 50 40 30 20 10 0 1 2 3 4 5 6 7 8 Group number 9 1 t: median = 41 (out of 64) Total: median = 74% (last semester median = 98%) 10 11 12

Course administration Latest thread library score 70 Thread library scores 60 50 40 30 20 10 0 2. 12 2. 13 2. 14 2. 15 2. 16 2. 17 Initial submit date 2. 17 2. 18 1 t: median = 41 (out of 64) Total: median = 74% (last semester median = 98%) 2. 18 2. 19

Course administration ê Next week ê I will be out of town ê Mid-term exam on Tuesday ê Amre will proctor exam ê No discussion sections ê Thursday lecture cancelled ê Project 2 out on Thursday ê Any questions about exam?

Course administration ê Project 2 ê ê Posted on the web next Thursday (February 28 th) Write a virtual memory manager Manage address spaces and page faults Due 4 weeks from today (March 20 th) ê Comparison to Project 1 ê Less difficult concepts (no synchronization) ê Lots of bookkeeping and corner cases ê No solution to compare to (e. g. thread. o)

4. Multi-level translation ê Standard page table ê Just a flat array of page table entries VA={b 31, b 30, …, b 12, b 11, …, b 1, b 0} High-order bits (Page number) Low-order bits (offset) Used to index into table

4. Multi-level translation ê Multi-level page table ê Use a tree instead of an array VA={b 31, b 30, …, b 22, b 21, …, b 12, b 11, …, b 1, b 0} Level 1 Level 2 Low-order bits (offset) Used to index into table 2 Used to index into table 1 What is stored in the level 1 page table? If valid? If invalid?

4. Multi-level translation ê Multi-level page table ê Use a tree instead of an array VA={b 31, b 30, …, b 22, b 21, …, b 12, b 11, …, b 1, b 0} Level 1 Level 2 Low-order bits (offset) Used to index into table 2 Used to index into table 1 What is stored in the level 2 page table? If valid? If invalid?

Two-level tree Level 1 Level 2 0 1 … NULL 1023 ? 0: Phys. Page, Res, Prot 1: Phys. Page, Res, Prot … … ? ? 1023: Phys. Page, Res, Prot VA={b 31, b 30, …, b 22, b 21, …, b 12, b 11, …, b 1, b 0} Level 1 Level 2 Offset

Two-level tree Level 1 Level 2 0 1 … NULL 1023 0: Phys. Page, Res, Prot 1: Phys. Page, Res, Prot … 1023: Phys. Page, Res, Prot How does this save space?

Two-level tree Level 1 Level 2 0 1 … NULL 1023 0: Phys. Page, Res, Prot 1: Phys. Page, Res, Prot … 1023: Phys. Page, Res, Prot What changes on a context switch?

Multi-level translation pros and cons + Space-efficient for sparse address spaces + Easy memory allocation + Easy sharing – What is the downside? Two extra lookups per reference (read level 1 PT, then read level 2 PT) (memory accesses just got really slow)

Translation look-aside buffer ê Aka the “TLB” ê Hardware cache from CPS 104 ê Maps virtual page #s to physical page #s ê On cache hit, get PTE very quickly ê On miss use page table, store mapping, restart instruction ê What happens on a context switch? ê Have to flush the TLB ê Takes time to rewarm the cache ê As in life, context switches may be expensive

Replacement ê Think of physical memory as a cache ê What happens on a cache miss? ê Page fault ê Must decide what to evict ê Goal: reduce number of misses

Review of replacement algorithms 1. Random ê Easy implementation, not great results 2. FIFO (first in, first out) ê Replace page that came in longest ago ê Popular pages often come in early ê Problem: doesn’t consider last time used 3. OPT (optimal) ê Replace the page that won’t be needed for longest time ê Problem: requires knowledge of the future

Review of replacement algorithms ê LRU (least-recently used) ê Use past references to predict future ê Exploit “temporal locality” ê Problem: expensive to implement exactly ê Why? ê Either have to keep sorted list ê Or maintain time stamps + scan on eviction ê Update info on every access (ugh)

LRU ê LRU is just an approximation of OPT ê Could try approximating LRU instead ê Don’t have to replace oldest page ê Just replace an old page

Clock ê Approximates LRU ê What can the hardware give us? ê “Reference bit” for each PTE ê Set each time page is accessed ê Why is this done in hardware? ê May be slow to do in software

Clock ê Approximates LRU ê What can the hardware give us? ê “Reference bit” for each PTE ê Set each time page is accessed ê What do “old” pages look like to OS? ê Clear all bits ê Check later to which are set

Clock Time 0: clear reference bit for page. . . Time t: examine reference bit ê Splits pages into two classes ê Those that have been touched lately ê Those that haven’t been touched lately ê Clearing all bits simultaneously is slow ê Try to spread work out over time

Clock A Physical page 0 Physical page 1 Physical page 2 E PP VP Physical page 3 PP VP Physical page 4 D PP VP = Resident virtual pages PP VP C B

Clock A Physical page 0 Physical page 1 Physical page 2 E PP VP Physical page 3 PP VP Physical page 4 D When you need to evict a page: 1) Check physical page pointed to by clock hand PP VP C B

Clock A Physical page 0 Physical page 1 Physical page 2 E PP VP Physical page 3 PP VP Physical page 4 D B PP VP C When you need to evict a page: 2) If reference=0, page hasn’t been touched in a while. Evict.

Clock A Physical page 0 Physical page 1 Physical page 2 E PP VP Physical page 3 PP VP Physical page 4 D B PP VP C When you need to evict a page: 3) If reference=1, page has been accessed since last sweep. What to do?

Clock A Physical page 0 Physical page 1 Physical page 2 E PP VP Physical page 3 PP VP Physical page 4 D B PP VP C When you need to evict a page: 3) If reference=1, page has been accessed since last sweep. Set reference=0. Rotate clock hand. Try next page.

Clock ê Does this cause an infinite loop? ê No. ê First sweep sets all to 0, evict on next sweep ê What about new pages? ê Put behind clock hand ê Set reference bit to 1 ê Maximizes chance for page to stay in memory

Paging out ê What can we do with evicted pages? ê Write to disk ê When don’t you need to write to disk? ê Disk already has data (page is clean) ê Can recompute page content (zero page)

Paging out ê Why set the dirty bit in hardware? ê If set on every store, too slow for software ê Why not write to disk on each store? ê Too slow ê Better to defer work ê You might not have to do it! (except in 110)

Paging out ê When does work of writing to disk go away? ê If you store to the page again ê If the owning process exits before eviction ê Project 2: other work you can defer ê Initializing a page with zeroes ê Taking faults

Paging out ê Faulted-in page must wait for disk write ê Can we avoid this work too? ê Evict clean (non-dirty) pages first ê Write out pages during idle periods ê Project 2: don’t do either of these!

Hardware page table info ê What should go in a PTE? Protection Physical page # Resident (read/write) Set by OS to control translation. Checked by MMU on each access. Set by OS to control access. Checked by MMU on each access. Dirty Reference Set by MMU Set by when page is MMU used. Used by when OS to see if page is modified. page has been referenced. Used by OS to see if page is decisions? modified. What bits does a MMU need to make access MMU needs to know if resident, readable, or writable. Do we really need a resident bit? No, if non-resident, set R=W=0.

MMU algorithm if (VP # is invalid || non-resident || protected) { trap to OS fault handler } else { physical page = page. Table[virtual page]. phys. Page. Num physical address = {physical page}{offset} page. Table[virtual page]. referenced = 1 if (access is write) { page. Table[virtual page]. dirty = 1 } } Project 2: infrastructure performs MMU functions Note: P 2 page table entry definition has no dirty/reference bits

Hardware page table entries ê Do PTEs need to store disk block nums? ê No ê Only the OS needs this (the MMU doesn’t) ê What per page info does OS maintain? ê Which virtual pages are valid ê On-disk locations of virtual pages

Hardware page table entries ê Do we really need a dirty bit? ê Claim: OS can emulate at a reasonable overhead. ê How can OS emulate the dirty bit? ê Keep the page read-only ê MMU will fault on a store ê OS/you now know that the page is dirty ê Do we need to fault on every store? ê No. After first store, set page writable ê When do we make it read-only again? ê When it’s clean (e. g. written to disk and paged in)

Hardware page table entries ê Do we really need a reference bit? ê Claim: OS can emulate at a reasonable overhead. ê How can OS emulate the reference bit? ê Keep the page unreadable ê MMU will fault on a load/store ê OS/you now knows that the page has been referenced ê Do we need to fault on every load/store? ê No. After first load/store, set page readable

Application’s perspective ê VM system manages page permissions ê Application is totally unaware of faults, etc ê Most OSes allow apps to request page protections ê E. g. make their code pages read-only ê Project 2 ê App has no control over page protections ê App assumes all pages are read/writable