CPRE 583 Reconfigurable Computing Lecture 2 8272010 VHDL

CPRE 583 Reconfigurable Computing Lecture 2: 8/27/2010 (VHDL Overview 1 ) Instructor: Dr. Phillip Jones (phjones@iastate. edu) Reconfigurable Computing Laboratory Iowa State University Ames, Iowa, USA http: //class. ece. iastate. edu/cpre 583/ 1 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University

Overview • Mini Literary Survey • VHDL review 1 • MP 1 2 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University

Literary Survey • Start with searching for papers from 2007 -2010 on IEEE Xplorer • Find popular cross references for each area • For each area try to identify 1 good survey papers • For each area – Identify 2 -3 core Problems/issues – For each problem identify 2 -3 Approaches for addressing – For each approach identify 1 -2 papers that Implement the approach. Iowa State University 3 - CPRE 583 (Reconfigurable Computing): VHDL overview 1

Literary Survey: Example Structure Hardware Accelerated Bioinformatics P 2 P 1 A 1 I 1 A 2 I 1 I 2 P 3 A 1 A 2 I 1 I 1 A 2 I 1 • 5 -10 page write up on your survey tree 4 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University

VHDL basics • VHDL: (V)HSIC (H)ardware (D)escription (L)anguage – VHSIC: (V)ery (H)igh (S)peed (I)ntegrated (C)ircuit • It is NOT a programming language!!! • It is a Hardware Description Language (HDL) • Conceptually VERY different form C, C++ 5 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University

Some Key Differences from C • C is inherently sequential (serial), one statement executed at a time • VHDL is inherently concurrent (parallel), many statements execute (simulate) at a time 6 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University

Some Key Differences from C C example VHDL example Initially: A, B, C, X, Y, Z, Ans =1 A=B+C X=Y+Z Ans = A + X Current Values: A=1 B=1 C=1 X=1 Y=1 Z=1 Ans = 1 7 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 A <= B + C X <= Y + Z Ans <= A + X Current Values: A=1 B=1 C=1 X=1 Y=1 Z=1 Ans = 1 Iowa State University

Some Key Differences from C C example VHDL example Initially: A, B, C, X, Y, Z, Ans =1 A=B+C X=Y+Z Ans = A + X Current Values: A=2 B=1 C=1 X=1 Y=1 Z=1 Ans = 1 8 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 A <= B + C X <= Y + Z Ans <= A + X Current Values: A=1 B=1 C=1 X=1 Y=1 Z=1 Ans = 1 Iowa State University

Some Key Differences from C C example VHDL example Initially: A, B, C, X, Y, Z, Ans =1 A=B+C X=Y+Z Ans = A + X Current Values: A=2 B=1 C=1 X=2 Y=1 Z=1 Ans = 1 9 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 A <= B + C X <= Y + Z Ans <= A + X Current Values: A=1 B=1 C=1 X=1 Y=1 Z=1 Ans = 1 Iowa State University

Some Key Differences from C C example VHDL example Initially: A, B, C, X, Y, Z, Ans =1 A=B+C X=Y+Z Ans = A + X Current Values: A=2 B=1 C=1 X=2 Y=1 Z=1 Ans = 4 10 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 A <= B + C X <= Y + Z Ans <= A + X Current Values: A=1 B=1 C=1 X=1 Y=1 Z=1 Ans = 1 Iowa State University

Some Key Differences from C VHDL example C example Initially: A, B, C, X, Y, Z, Ans =1 A=B+C X=Y+Z Ans = A + X A <= B + C X <= Y + Z Ans <= A + X “Simulates in parallel ever delta time step” Current Values: A=2 B=1 Show impact C=1 Of changing X=2 Order of statements Y=1 Z=1 Ans = 4 11 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Current Values: A=1 B=1 C=1 X=1 Y=1 Z=1 Ans = 1 Iowa State University

Some Key Differences from C VHDL example C example Initially: A, B, C, X, Y, Z, Ans =1 A=B+C X=Y+Z Ans = A + X Snap shot after input change A <= B + C X <= Y + Z Ans <= A + X “Simulates in parallel ever delta time step” Current Values: A=2 B=1 C=1 X=2 Y=1 Z=1 Ans = 4 12 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Current Values: A=1 B=1 C=1 X=1 Y=1 Z=1 Ans = 1 Iowa State University

Some Key Differences from C VHDL example C example Initially: A, B, C, X, Y, Z, Ans =1 A=B+C X=Y+Z Ans = A + X A <= B + C X <= Y + Z Ans <= A + X “Simulates in parallel ever delta time step” Current Values: A=2 B=1 C=1 X=2 Y=1 Z=1 Ans = 4 13 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Current Values: A=2 B=1 C=1 X=2 Y=1 Z=1 Ans = 2 Iowa State University

Some Key Differences from C VHDL example C example Initially: A, B, C, X, Y, Z, Ans =1 A=B+C X=Y+Z Ans = A + X A <= B + C X <= Y + Z Ans <= A + X “Simulates in parallel ever delta time step” Current Values: A=2 B=1 C=1 X=2 Y=1 Z=1 Ans = 4 Different 14 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Current Values: A=2 B=1 C=1 X=2 Y=1 Z=1 Ans = 2 Iowa State University

Some Key Differences from C VHDL example C example Initially: A, B, C, X, Y, Z, Ans =1 A=B+C X=Y+Z Ans = A + X Snap shot after input change A <= B + C X <= Y + Z Ans <= A + X “Simulates in parallel ever delta time step” Current Values: A=2 B=1 C=1 X=2 Y=1 Z=1 Ans = 4 15 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Current Values: A=2 B=1 C=1 X=2 Y=1 Z=1 Ans = 2 Iowa State University

Some Key Differences from C VHDL example C example Initially: A, B, C, X, Y, Z, Ans =1 A=B+C X=Y+Z Ans = A + X A <= B + C X <= Y + Z Ans <= A + X “Simulates in parallel ever delta time step” Current Values: A=2 B=1 C=1 X=2 Y=1 Z=1 Ans = 4 16 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Current Values: A=2 B=1 C=1 X=2 Y=1 Z=1 Ans = 2 Iowa State University

Some Key Differences from C VHDL example C example Initially: A, B, C, X, Y, Z, Ans =1 A=B+C X=Y+Z Ans = A + X A <= B + C X <= Y + Z Ans <= A + X “Simulates in parallel ever delta time step” Current Values: A=2 B=1 C=1 X=2 Y=1 Z=1 Ans = 4 17 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Current Values: A=2 B=1 C=1 X=2 Y=1 Z=1 Ans = 4 Iowa State University

Corresponding circuit VHDL example Initially: A, B, C, X, Y, Z, Ans =1 A <= B + C X <= Y + Z Ans <= A + X “Simulates in parallel ever delta time step” 18 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University

Corresponding circuit VHDL example Initially: A, B, C, X, Y, Z, Ans =1 A <= B + C X <= Y + Z Ans <= A + X “Simulates in parallel ever delta time step” B(1) C(1) + A(1) + Y(1) Z(1) + 19 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Ans(1) X(1) Iowa State University

Corresponding circuit VHDL example Initially: A, B, C, X, Y, Z, Ans =1 A <= B + C X <= Y + Z Ans <= A + X “Simulates in parallel ever delta time step” B(1) C(1) + A(2) + Y(1) Z(1) + 20 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Ans(2) X(2) Iowa State University

Corresponding circuit VHDL example Initially: A, B, C, X, Y, Z, Ans =1 A <= B + C X <= Y + Z Ans <= A + X “Simulates in parallel ever delta time step” B(1) C(1) + A(2) + Y(1) Z(1) + 21 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Ans(4) X(2) Iowa State University

Corresponding circuit (More realistic) VHDL example Initially: A, B, C, X, Y, Z, Ans =1 A <= B + C after 2 ns X <= Y + Z after 2 ns Ans <= A + X after 2 ns “Simulates in parallel ever delta time step” B(1) C(1) Y(1) Z(1) + A(1) 2 ns + + X(1) Ans(1) 2 ns 22 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University

Corresponding circuit (More realistic) VHDL example Initially: A, B, C, X, Y, Z, Ans =1 A <= B + C after 2 ns X <= Y + Z after 2 ns Ans <= A + X after 2 ns “Simulates in parallel ever delta time step” B(1) C(1) Y(1) Z(1) + A(2) 2 ns + + X(2) Ans(2) 2 ns 23 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University

Corresponding circuit (More realistic) VHDL example Initially: A, B, C, X, Y, Z, Ans =1 A <= B + C after 2 ns X <= Y + Z after 2 ns Ans <= A + X after 2 ns “Simulates in parallel ever delta time step” B(1) C(1) Y(1) Z(1) + A(2) 2 ns + + X(2) Ans(4) 2 ns 24 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University

Typical Structure of a VHDL File LIBRARY ieee; ENTITY test_circuit IS PORT(B, C, Y, Z, Ans); END test_circuit; Include Libraries Define component name and Input/output ports Declare internal ARCHITECTURE structure OF test_circuit IS signal A : std_logic_vector(7 downto 0); signals, signal X : std_logic_vector(7 downto 0); components BEGIN A <= B + C; X <= Y + Z; Ans <= A + X; Implement components functionality END 25 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University

Process • Process provide a level serialization in VHDL (e. g. variables, clocked processes) • Help separate and add structure to VHDL design 26 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University

Process Example BEGIN My_process_1 : process (A, B, C, X, Y, Z) Begin Sensitivity list: specify inputs to the A <= B + C; process. Process is updated when X <= Y + Z; a specified input changes Ans <= A + X; End My_process_1; My_process_2 : process (B, X, Y, Ans 1) Begin A <= B + 1; X <= B + Y; Ans 2 <= Ans 1 + X; End My_process_2; END; 27 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University

Process Example (Multiple Drivers) BEGIN My_process_1 : process (A, B, C, X, Y, Z) Begin A <= B + C; X <= Y + Z; Ans <= A + X; End My_process_1; My_process_2 : process (B, X, Y, Ans 1) Begin A <= B + 1; X <= B + Y; Ans 2 <= Ans 1 + X; End My_process_2; A signal can only be Driven (written) by one process. But can be read by many Compile or simulator may give a “multiple driver” Error or Warning message END; 28 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University

Process Example (Multiple Drivers) BEGIN My_process_1 : process (A, B, C, X, Y, Z) Begin A <= B + C; X <= Y + Z; Ans <= A + X; End My_process_1; My_process_2 : process (B, X, Y, Ans 1) Begin Maybe A, X were suppose to be A 1, X 1. Cut A 1 <= B + 1; and paste error. Or may need to rethink X 1 <= B + Y; Hardware structure to remove multiple driver Ans 2 <= Ans 1 + X; issue. End My_process_2; END; 29 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University

Process Example (if-statement) BEGIN My_process_1 : process (A, B, C, X, Y, Z) Begin if (B = 0) then C <= A + B; Z <= X + Y; Ans 1 <= A + X; else C <= 1; Z <= 0; Ans 1 <= 1; end if; End My_process_1; END; 30 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University

Clock Process Example BEGIN My_process_1 : process (clk) Begin IF (clk’event and clk = ‘ 1’) THEN C <= A or B; Z <= X or Y; Ans <= C and Z; END IF; circuit not clocked End My_process_1; A() B() or C() and X() Y() or Ans() Z() END; 31 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University

Clock Process Example BEGIN My_process_1 : process (clk) Begin IF (clk’event and clk = ‘ 1’) THEN C <= A or B; Z <= X or Y; Ans <= C and Z; END IF; circuit with clock End My_process_1; A() B() or D Flip-Flop DFF Register C() and X() Y() END; or Ans() Z() clk 32 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University

Clock Process Example BEGIN My_process_1 : process (clk) Begin IF (clk’event and clk = ‘ 1’) THEN C <= A or B; Z <= X or Y; Ans <= C and Z; END IF; End My_process_1; clk END; circuit with clock A() B() or C() and X() Y() 33 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 or Ans() Z() Iowa State University

Clock Process Example 2 BEGIN My_process_1 : process (clk) Begin IF (clk’event and clk = ‘ 1’) THEN C <= A xor B; Z <= X or Y; Ans <= C xor Z; END IF; End My_process_1; clk END; circuit with clock A() B() xor C() xor X() Y() 34 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 or Ans() Z() Iowa State University

Clock Process Example 2 (Answer) BEGIN My_process_1 : process (clk) Begin IF (clk’event and clk = ‘ 1’) THEN C <= A xor B; Z <= X or Y; Ans <= C xor Z; END IF; End My_process_1; clk END; circuit with clock A() B() xor C() xor X() Y() 35 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 or Ans() Z() Iowa State University

VHDL Constructs • • Entity Process Signal, Variable, Constants, Integers Array, Record VHDL on-line tutorials: http: //www. seas. upenn. edu/~ese 201/vhdl_primer. html http: //www. vhdl-online. de/tutorial/ 36 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University

Signals and Variables • Signals – Updated at the end of a process – Have file scope • Variables – Updated instantaneously – Have process scope VHDL on-line tutorials: http: //www. seas. upenn. edu/~ese 201/vhdl_primer. html http: //www. vhdl-online. de/tutorial/ 37 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University

std_logic, std_logic_vector • Very common data types • std_logic – Single bit value – Values: U, X, 0, 1, Z, W, H, L, – Example: signal A : std_logic; • A <= ‘ 1’; • Std_logic_vector: is an array of std_logic – Example: signal A : std_logic_vector (4 downto 0); • A <= x“ 00 Z 001” VHDL on-line tutorials: http: //www. seas. upenn. edu/~ese 201/vhdl_primer. html http: //www. vhdl-online. de/tutorial/ 38 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University

Std_logic values • Std_logic values – U : Uninitialized (signal has not been assigned a value yet) – X : Unknow (2 drivers one ‘ 0’ one ‘ 1’) – H : weak ‘ 1’ (example: model pull-up resister) • I have never used this value – L : weak ‘ 0’ Time step 0 39 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University

Std_logic values • Std_logic values – U : Uninitialized (signal has not been assigned a value yet) – X : Unknow (2 drivers one ‘ 0’ one ‘ 1’) – H : weak ‘ 1’ (example: model pull-up resister) • I have never used this value – L : weak ‘ 0’ 1 U U U Time step 0 40 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University

Std_logic values • Std_logic values – U : Uninitialized (signal has not been assigned a value yet) – X : Unknow (2 drivers one ‘ 0’ one ‘ 1’) – H : weak ‘ 1’ (example: model pull-up resister) • I have never used this value – L : weak ‘ 0’ 0 1 U U Time step 1 41 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University

Std_logic values • Std_logic values – U : Uninitialized (signal has not been assigned a value yet) – X : Unknow (2 drivers one ‘ 0’ one ‘ 1’) – H : weak ‘ 1’ (example: model pull-up resister) • I have never used this value – L : weak ‘ 0’ 1 0 1 U Time step 2 42 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University

Std_logic values • Std_logic values – U : Uninitialized (signal has not been assigned a value yet) – X : Unknow (2 drivers one ‘ 0’ one ‘ 1’) – H : weak ‘ 1’ (example: model pull-up resister) • I have never used this value – L : weak ‘ 0’ 1 1 0 1 Time step 3 43 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University

Std_logic values • Std_logic values – U : Uninitialized (signal has not been assigned a value yet) – X : Unknow (2 drivers one ‘ 0’ one ‘ 1’) – H : weak ‘ 1’ (example: model pull-up resister) • I have never used this value – L : weak ‘ 0’ 1 0 1 1 0 X 1 Time step 3 44 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University

Std_logic values • Std_logic values – U : Uninitialized (signal has not been assigned a value yet) – X : Unknow (2 drivers one ‘ 0’ one ‘ 1’) – H : weak ‘ 1’ (example: model pull-up resister) • I have never used this value – L : weak ‘ 0’ 1 0 1 1 0 Time step 3 45 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 X 1 0 1 Iowa State University

Std_logic values • Std_logic values – U : Uninitialized (signal has not been assigned a value yet) – X : Unknow (2 drivers one ‘ 0’ one ‘ 1’) – H : weak ‘ 1’ (example: model pull-up resister) • I have never used this value – L : weak ‘ 0’ 1 0 0 1 1 Time step 3 46 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 X X X 1 Iowa State University

Std_logic values • Std_logic values – U : Uninitialized (signal has not been assigned a value yet) – X : Unknow (2 drivers one ‘ 0’ one ‘ 1’) – H : weak ‘ 1’ (example: model pull-up resister) • I have never used this value – L : weak ‘ 0’ ‘ 1’ Pull-up resistor Time step 0 47 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University

Std_logic values • Std_logic values – U : Uninitialized (signal has not been assigned a value yet) – X : Unknow (2 drivers one ‘ 0’ one ‘ 1’) – H : weak ‘ 1’ (example: model pull-up resister) • I have never used this value – L : weak ‘ 0’ ‘ 1’ 0 U H Pull-up resistor U Time step 0 48 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University

Std_logic values • Std_logic values – U : Uninitialized (signal has not been assigned a value yet) – X : Unknow (2 drivers one ‘ 0’ one ‘ 1’) – H : weak ‘ 1’ (example: model pull-up resister) • I have never used this value – L : weak ‘ 0’ ‘ 1’ 1 0 H Pull-up resistor 1 Time step 1 49 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University

Std_logic values • Std_logic values – U : Uninitialized (signal has not been assigned a value yet) – X : Unknow (2 drivers one ‘ 0’ one ‘ 1’) – H : weak ‘ 1’ (example: model pull-up resister) • I have never used this value – L : weak ‘ 0’ ‘ 1’ Pull-up resistor Resolution(H, 0) = 0 0 1 Time step 2 50 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University

Pre-defined VHDL attributes • • mysignal’event (mysignal changed value) mysignal’high (highest value of mysignal’s type) mysignal’low Many other attributes – http: //www. cs. umbc. edu/help/VHDL/summary. html 51 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University

Singal vs Varible scope • Signal: global to file • Variable: local to process My_process_1 : process (B, C, Y) Begin A <= B + C; Z <= Y + C; End My_process_1; My_process_2 : process (B, X, Y, Ans 1) Begin X <= Z + 1; Ans <= B + Y; End My_process_2; VHDL on-line tutorials: http: //www. seas. upenn. edu/~ese 201/vhdl_primer. html http: //www. cs. umbc. edu/help/VHDL/summary. html http: //www. vhdl-online. de/tutorial/ 52 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University

Singal vs Varible scope • Signal: global to file • Variable: local to process Each var. Z are local to their process. Completely independent My_process_1 : process (B, C, Y) Begin A <= B + C; var. Z <= Y + C; End My_process_1; My_process_2 : process (B, X, Y, Ans 1) Begin X <= var. Z + 1; Ans <= B + Y; End My_process_2; VHDL on-line tutorials: http: //www. seas. upenn. edu/~ese 201/vhdl_primer. html http: //www. cs. umbc. edu/help/VHDL/summary. html http: //www. vhdl-online. de/tutorial/ 53 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University

Arrays and Records • Arrays: Group signals of the same type together • Records: Group signal of different types together VHDL on-line tutorials: http: //www. seas. upenn. edu/~ese 201/vhdl_primer. html http: //www. vhdl-online. de/tutorial/ 54 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University

Array Example (Delay Shift Register) flag_in flag_1 flag_2 flag_3 flag_out BEGIN My_process_1 : process (clk) Begin IF (clk’event and clk = ‘ 1’) THEN flag_1 <= flag_in; flag_2 <= flag_1; flag_3 <= flag_2; END IF; End My_process_1; flag_out <= flag_3 END; VHDL on-line tutorials: http: //www. seas. upenn. edu/~ese 201/vhdl_primer. html http: //www. vhdl-online. de/tutorial/ 55 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University

Array Example (Delay Shift Register) flag_in flag_1 flag_20 flag_out BEGIN My_process_1 : process (clk) Begin IF (clk’event and clk = ‘ 1’) THEN flag_1 <= flag_in; flag_2 <= flag_1; flag_20 <= flag_19; END IF; End My_process_1; flag_out <= flag_20 END; VHDL on-line tutorials: http: //www. seas. upenn. edu/~ese 201/vhdl_primer. html http: //www. vhdl-online. de/tutorial/ 56 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University

Array Example (Delay Shift Register) flag_in flag_1 flag_20 flag_out type flag_reg_array is array (DELAY-1 downto 0) of std_logic; signal flag_reg : flag_reg_array; BEGIN My_process_1 : process (clk) Begin IF (clk’event and clk = ‘ 1’) THEN flag_reg(flag_reg'high downto 0) <= flag_reg(flag_reg'high-1 downto 0) & flag_in; END IF; End My_process_1; flag_out <= flag_reg(flag_reg'high); END; 57 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University

Array Example (Delay Shift Register) flag_reg(flag_reg'high downto 0)<= flag_reg(flag_reg'high-1 downto 0) & flag_in; flag_in flag(0) 0 1 flag_in 0 flag(0) 0 1 flag(1) flag_in 1 flag(1) 0 flag(0) 1 flag(2) flag_out 1 flag(1) 0 58 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 flag(2) flag_out 0 Iowa State University