CPRE 583 Reconfigurable Computing Lecture 12 Wed 9302011

CPRE 583 Reconfigurable Computing Lecture 12: Wed 9/30/2011 (FPGA Features & Convey Computer HC-1) Instructor: Dr. Phillip Jones (phjones@iastate. edu) Reconfigurable Computing Laboratory Iowa State University Ames, Iowa, USA http: //class. ee. iastate. edu/cpre 583/ 1 - CPRE 583 (Reconfigurable Computing): FPGA Features and Convey Computer HC-1 Iowa State University

Announcements/Reminders • Mini literary survey due Fri 9/30 midnight (5 -10 pages). • First exam: next Fri 10/7 in class (take home due following Monday at midnight) – In class portion closed notes • Distance students: I’ll send an email with how you’ll take this. – Take home, open everything (no interacting with others) • Project Teams: Form by Monday 10/10 • MP 2 due Friday 10/14 • Project Advertising/Discussion (Wed 10/5 in class) – Blackboard discussion group to be up this evening – Wed 10/5 in class: I will allocated 5 minutes to each person who would like to present 2 -3 slides about their topic to recruit team members. If distances students would like to advertise, then I would be happy to present your slides. 2 - CPRE 583 (Reconfigurable Computing): FPGA Features and Convey Computer HC-1 Iowa State University

Project Grading Breakdown • 50% Final Project Demo • 30% Final Project Report – 20% of your project report grade will come from your 5 -6 project updates. Friday’s midnight • 20% Final Project Presentation 3 - CPRE 583 (Reconfigurable Computing): FPGA Features and Convey Computer HC-1 Iowa State University

Projects Ideas: Relevant conferences • • • FPL FPT FCCM FPGA DAC ICCAD Reconfig RTSS RTAS ISCA • • Micro Super Computing HPCA IPDPS 4 - CPRE 583 (Reconfigurable Computing): FPGA Features and Convey Computer HC-1 Iowa State University

Projects: Target Timeline • Teams Formed and Topic: Mon 10/10 – Project idea in Power Point 3 -5 slides • Motivation (why is this interesting, useful) • What will be the end result • High-level picture of final product – Project team list: Name, Responsibility • High-level Plan/Proposal: Fri 10/14 – Power Point 5 -10 slides (presentation to class Wed 10/19) • System block diagrams • High-level algorithms (if any) • Concerns – Implementation – Conceptual • Related research papers (if any) 5 - CPRE 583 (Reconfigurable Computing): FPGA Features and Convey Computer HC-1 Iowa State University

Projects: Target Timeline • Work on projects: 10/19 - 12/9 – Weekly update reports • More information on updates will be given • Presentations: Finals week – Present / Demo what is done at this point – 15 -20 minutes (depends on number of projects) • Final write up and Software/Hardware turned in: Day of final (TBD) 6 - CPRE 583 (Reconfigurable Computing): FPGA Features and Convey Computer HC-1 Iowa State University

Initial Project Proposal Slides (5 -10 slides) • Project team list: Name, Responsibility (who is project leader) – Team size: 3 -4 (5 case-by-case) • Project idea • Motivation (why is this interesting, useful) • What will be the end result • High-level picture of final product • High-level Plan – Break project into mile stones • Provide initial schedule: I would initially schedule aggressively to have project complete by Thanksgiving. Issues will pop up to cause the schedule to slip. – System block diagrams – High-level algorithms (if any) – Concerns • Implementation • Conceptual • Research papers related to you project idea 7 - CPRE 583 (Reconfigurable Computing): FPGA Features and Convey Computer HC-1 Iowa State University

Weekly Project Updates • The current state of your project write up – Even in the early stages of the project you should be able to write a rough draft of the Introduction and Motivation section • The current state of your Final Presentation – Your Initial Project proposal presentation (Due Wed 10/19). Should make for a starting point for you Final presentation • What things are work & not working • What roadblocks are you running into 8 - CPRE 583 (Reconfigurable Computing): FPGA Features and Convey Computer HC-1 Iowa State University

Common Questions 9 - CPRE 583 (Reconfigurable Computing): FPGA Features and Convey Computer HC-1 Iowa State University

Overview • FPGA Feature and resources • Convey Computer HC-1 10 - CPRE 583 (Reconfigurable Computing): FPGA Features and Convey Computer HC-1 Iowa State University

FPGA Features in General • • LUTs DFFs Block. RAM (on-chip memory) Multipliers CPU processor cores Clock generators and managers Many IP cores: Xilinx provides through Coregen 11 - CPRE 583 (Reconfigurable Computing): FPGA Features and Convey Computer HC-1 Iowa State University

Computational Fabric - LUT A B C D ABCD Z 0000 0001 4 -LUT ABCD Z 0000 0 0001 0 1111 1110 1111 LUT = Look up Table Z ABCD Z 0000 0 0001 1 0 1 1110 1111 1 1 ABCD X 000 X 001 X 010 Z 0 1 0 X 101 X 110 X 111 0 1 1 B A B C D AND Z A B C D OR Z 12 - CPRE 583 (Reconfigurable Computing): FPGA Features and Convey Computer HC-1 C D 1 2: 1 0 Mux Z Iowa State University

Computational Fabric - DFF A B C D Z(t) Z(t+1) 4 -LUT DFF = D Flip Flop 13 - CPRE 583 (Reconfigurable Computing): FPGA Features and Convey Computer HC-1 Iowa State University

LUTs and DFF • How many and how large is each – Look at Xilinx Virtex-5 family overview • 70 FX: • 330 LXT 14 - CPRE 583 (Reconfigurable Computing): FPGA Features and Convey Computer HC-1 Iowa State University

Block. Ram: On-chip Memory Embedded Memory 8 96 bits, 300 MHz 12 15 - CPRE 583 (Reconfigurable Computing): FPGA Features and Convey Computer HC-1 Iowa State University

Block. Ram: On-chip Memory Embedded Memory 8 18 Kbits, 550 MHz Dedicated 12 memory block 16 - CPRE 583 (Reconfigurable Computing): FPGA Features and Convey Computer HC-1 Iowa State University

Block. Ram: On-chip Memory • How many and how large is each – Look at Xilinx Virtex-5 family overview • 70 FX: • 330 LXT 17 - CPRE 583 (Reconfigurable Computing): FPGA Features and Convey Computer HC-1 Iowa State University

Hard-core 18 x 18 Multipliers Multiplication 18 x 18 multiply Type # LUTs Latency Speed LUT ~400 5 clks 380 MHz Dedicated 18 x 18 Multiplier 0 3 clks 450 MHz Virtex-5 (6 -LUTs) Very rough estimate of Silicon area comparison (assuming SX 95 and. LX 110 have about the same die size) 6 -LUT 18 x 18 Multiplier 6 -LUT In other word you can replace one LUT based 18 x 18 multiplier With 100 dedicated 18 x 18 Multipliers!!! 18 - CPRE 583 (Reconfigurable Computing): FPGA Features and Convey Computer HC-1 Iowa State University

Hard-core multipliers • How many and how large is each – Look at Xilinx Virtex-5 family overview • 70 FX: • 330 LXT: 19 - CPRE 583 (Reconfigurable Computing): FPGA Features and Convey Computer HC-1 Iowa State University

Hard-core or Soft-core Processors Processor Power. PC hard-core • 500 MHz • Super scalor • Highspeed 2 x 5 switch fabric Micro. Blaze soft-core • 250 MHz • Simple scalar 20 - CPRE 583 (Reconfigurable Computing): FPGA Features and Convey Computer HC-1 Iowa State University

Hard-core or Soft-core Processor • How to use – Xilinx EDK (Embedded Development Kit). – You will use for MP 3, and an in class demo of using EDK will be given 21 - CPRE 583 (Reconfigurable Computing): FPGA Features and Convey Computer HC-1 Iowa State University

Clock Generation: DCM and PLLs • Why? – Because you may corrupt packets, causing the OS to drop the packet before your application can see it • Tcpdump – Useful program for viewing low level network traffic – Typical need greater than regular user access • Example usage – sudo /usr/sbin/tcpdump -i eth 0 -v -s 0 -XX 22 - CPRE 583 (Reconfigurable Computing): FPGA Features and Convey Computer HC-1 Iowa State University

Xilinx IP Cores • Xilnx provides may IP core that can be used for your projects • Coregen is the tool that is used to configure and create an IP componet. • Take a quick look at Coregen – We will do an in class soon after exam 1 23 - CPRE 583 (Reconfigurable Computing): FPGA Features and Convey Computer HC-1 Iowa State University

Putting the pieces together System on Chip ADC DRAM Or SRAM Dedicated Logic Reconfigurable Logic Matrix Multiplier Coprocessor Ethernet MAC Data Buffer PID Controller 24 - CPRE 583 (Reconfigurable Computing): FPGA Features and Convey Computer HC-1 Sensor Motor Iowa State University

Platforms Available • The following platforms will be available for doing class projects – ML 507 (class’ board), ML 506 (DSP apps), ML 509 (high logic density) – RAVI Board (Altera-based) – Convey Computer 25 - CPRE 583 (Reconfigurable Computing): FPGA Features and Convey Computer HC-1 Iowa State University

ML 507 26 - CPRE 583 (Reconfigurable Computing): FPGA Features and Convey Computer HC-1 Iowa State University

RAVI Board 27 - CPRE 583 (Reconfigurable Computing): FPGA Features and Convey Computer HC-1 Iowa State University

Convey HC-1: Highlevel § § MC LX 155 MC LX 155 FPGA Based Compute Accelerator Pre-Defined Vector Instruction Set Shared Memory Programming Model ANSI C Support MC LX 155 § Socket Filler Module § Bridge FPGA § Implements FSB Protocol § Full Snoop Support Source: Convey Computer, 2008 Source: Xilinx Corporation, 2009 § § Accelerator Cache Memory 80 GB/s BW Snoop Coherent with System Memory Direct Cache Access CPU<->FPGA 28 - CPRE 583 (Reconfigurable Computing): FPGA Features and Convey Computer HC-1 Iowa State University

Next Lecture • Exam 1 review & Project Advertising 29 - CPRE 583 (Reconfigurable Computing): FPGA Features and Convey Computer HC-1 Iowa State University

Questions/Comments/Concerns • Write down – Main point of lecture – One thing that’s still not quite clear OR – If everything is clear, then give an example of how to apply something from lecture 30 - CPRE 583 (Reconfigurable Computing): FPGA Features and Convey Computer HC-1 Iowa State University

Lecture Notes 31 - CPRE 583 (Reconfigurable Computing): FPGA Features and Convey Computer HC-1 Iowa State University