CPRE 583 Reconfigurable Computing Lecture 1 Wed 8252009
CPRE 583 Reconfigurable Computing Lecture 1: Wed 8/25/2009 (Course Overview) Instructor: Dr. Phillip Jones (phjones@iastate. edu) Reconfigurable Computing Laboratory Iowa State University Ames, Iowa, USA http: //class. ece. iastate. edu/cpre 583/ 1 - ECp. E 583 (Reconfigurable Computing): Course overview Iowa State University
Class Introduction • Class Survey (by next class, phjones@iastate. edu) – Background (year in school, C programming, VHDL/Verilog, EE/CPRE background, ISU login ID) – What would you like to get from this class • Syllabus • Course Expectations – Reinforce research fundamentals – Asking the right question • VHDL handbook (source Synplicity) – http: //hapssupportnet. synplicity. com/download/VHDL-Handbook. pdf (quick ref) • VHDL online tutorials – http: //www. seas. upenn. edu/~ese 201/vhdl_primer. html – http: //www. vhdl-online. de/tutorial/ 2 - ECp. E 583 (Reconfigurable Computing): Course overview Iowa State University
What you should learn • Basic objectives and topics covered in this class. • VDHL is NOT a programming language. It is a means to describe hardware. 3 - ECp. E 583 (Reconfigurable Computing): Course overview Iowa State University
Main topics Agenda 1. Overview (4 Weeks) a. Reconfigurable HW b. VHDL 2. Computation Models (1. 5 Weeks) 3. Applications / Concerns of FPGAs (2 Weeks) 4. Mapping logic to FPGAs (3 Weeks) • Basic components of an FPGA (Chapter 1) • Overview of ways in which reconfigurable computing can be integrated into a system (Chapter 2) • Examples of reconfigurable systems (Chapter 3) 5. Case Studies (1 Week) • Managing the reconfiguration of systems? (Chapter 4) 4 - ECp. E 583 (Reconfigurable Computing): Course overview Iowa State University
Main topics Agenda 1. Overview (4 Weeks) a. Reconfigurable HW b. VHDL 2. Computation Models (1. 5 Weeks) opcode {+, -, AND, OR} A ALU B Behavior VHDL: ALU 3. Applications / Concerns compnt ALU (A, B, opcode, X) of FPGAs (2 Weeks) case opcode 4. Mapping logic to FPGAs when => op. Plus X <= A + B; (3 Weeks) when => op. Sub 5. Case Studies (1 Week) X <= A – B; when => op. AND X <= A and B; when => op. OR X <= A or B; end case; end component; 5 - ECp. E 583 (Reconfigurable Computing): Course overview X Structural VHDL: ALU component ALU (A, B, opcode, X) add. AB(A, B, Xadd); sub. AB(A, B, Xsub); and. AB(A, B, Xand); or. AB(A, B, Xor); 4: 1 mux(opcode, Xadd, Xor, Xand, Xor, X); end component; Iowa State University
Main topics Agenda opcode {+, -, AND, OR} 1. Overview (4 Weeks) a. Reconfigurable HW b. VHDL A ALU X B 2. Computation Models (1. 5 Weeks) ALU 3. Applications / Concerns of FPGAs (2 Weeks) 4. Mapping logic to FPGAs (3 Weeks) A 5. Case Studies (1 Week) add. AB sub. AB and. AB B or. AB 6 - ECp. E 583 (Reconfigurable Computing): Course overview opcode {+, -, AND, OR} Xadd 2 Xsub 4: 1 Xand Mux Xor Structural VHDL: ALU component ALU (A, B, opcode, X) add. AB(A, B, Xadd); sub. AB(A, B, Xsub); X and. AB(A, B, Xand); or. AB(A, B, Xor); 4: 1 mux(opcode, Xadd, Xor, Xand, Xor, X); end component; Iowa State University
Main topics Agenda 1. Overview (4 Weeks) a. Reconfigurable HW b. VHDL 2. Computation Models (1. 5 Weeks) 3. Applications / Concerns of FPGAs (2 Weeks) Abstraction that allows – Reasoning about computation • Correctness • Extraction of parallelism – Transformations for optimization – Guarantee Properties 4. Mapping logic to FPGAs (3 Weeks) Memory 5. Case Studies (1 Week) 7 - ECp. E 583 (Reconfigurable Computing): Course overview FPGA CPU Iowa State University
Main topics Agenda 1. Overview (4 Weeks) a. Reconfigurable HW b. VHDL 2. Computation Models (1. 5 Weeks) 3. Applications / Concerns of FPGAs (2 Weeks) Abstraction that allows – Reasoning about computation • Correctness • Extraction of parallelism – Transformations for optimization – Guarantee Properties 4. Mapping logic to FPGAs (3 Weeks) Memory 5. Case Studies (1 Week) 8 - ECp. E 583 (Reconfigurable Computing): Course overview Function 2 Function 1 Function 3 Function 4 Iowa State University
Main topics Agenda 1. Overview (4 Weeks) a. Reconfigurable HW b. VHDL 2. Computation Models (1. 5 Weeks) 3. Applications / Concerns of FPGAs (2 Weeks) Abstraction that allows – Reasoning about computation • Correctness • Extraction of parallelism – Transformations for optimization – Guarantee Properties 4. Mapping logic to FPGAs (3 Weeks) Memory 5. Case Studies (1 Week) 9 - ECp. E 583 (Reconfigurable Computing): Course overview Function 5 Function 1 Function 2 Function 3 Function 4 Memory Iowa State University
Main topics Agenda 1. Overview (4 Weeks) a. Reconfigurable HW b. VHDL 2. Computation Models (1. 5 Weeks) 3. Applications / Concerns of FPGAs (2 Weeks) 4. Mapping logic to FPGAs (3 Weeks) 5. Case Studies (1 Week) • Streaming Applications • Data Parallel Applications • Fix/Floating Point Computations • Performance Trade-offs • Fault Tolerance 10 - ECp. E 583 (Reconfigurable Computing): Course overview Iowa State University
Main topics Agenda X <= A+B; X <= A xor B; X <= A and B; X <= A or B; 1. Overview (4 Weeks) X A X A add. AB xor. AB and. AB or. AB a. Reconfigurable HW B B b. VHDL A B X 2. Computation Models 0 0 0 (1. 5 Weeks) 0 1 1 0 3. Applications / Concerns 1 0 1 1 0 0 of FPGAs (2 Weeks) 1 1 1 0 1 1 1 4. Mapping logic to FPGAs 2 -input Look Up Tables (LUTs) (3 Weeks) FPGA 5. Case Studies (1 Week) LUT LUT LUT LUT 11 - ECp. E 583 (Reconfigurable Computing): Course overview Iowa State University
Main topics Agenda X <= A+B; X <= A xor B; X <= A and B; X <= A or B; 1. Overview (4 Weeks) X A X A add. AB xor. AB and. AB or. AB a. Reconfigurable HW B B b. VHDL A B X 2. Computation Models 0 0 0 (1. 5 Weeks) 0 1 1 0 3. Applications / Concerns 1 0 1 1 0 0 of FPGAs (2 Weeks) 1 1 1 0 1 1 1 4. Mapping logic to FPGAs 2 -input Look Up Tables (LUTs) (3 Weeks) FPGA 5. Case Studies (1 Week) LUT add. AB LUT LUT LUT xor. AB and. AB LUT LUT or. AB LUT 12 - ECp. E 583 (Reconfigurable Computing): Course overview Iowa State University
Main topics Agenda 1. Overview (4 Weeks) a. Reconfigurable HW b. VHDL 2. Computation Models (1. 5 Weeks) 3. Applications / Concerns of FPGAs (2 Weeks) 4. Mapping logic to FPGAs (3 Weeks) Lectures on interesting uses of FPGAs. Ideally covering topics that the class would like to learn more about. Please give suggestions as the semester progresses. 5. Case Studies (1 Week) 13 - ECp. E 583 (Reconfigurable Computing): Course overview Iowa State University
Machine Problems (MPs) Agenda 1. Platform Introduction 2. Network String Matching 3. Image: PPC coprocessor 4. Final Projects(~6 weeks) 14 - ECp. E 583 (Reconfigurable Computing): Course overview Iowa State University
Machine Problems (MPs) Agenda 1. Platform Introduction ML 507 2. Network String Matching 3. Image: PPC coprocessor 4. Final Projects(~6 weeks) 15 - ECp. E 583 (Reconfigurable Computing): Course overview Iowa State University
Machine Problems (MPs) Agenda 1. Platform Introduction 2. Network String Matching 3. Image: PPC coprocessor 4. Final Projects(~6 weeks) 16 - ECp. E 583 (Reconfigurable Computing): Course overview Iowa State University
Machine Problems (MPs) Agenda 1. Platform Introduction 2. Network String Matching 3. Image: PPC coprocessor FPGA 4. Final Projects(~6 weeks) PC 17 - ECp. E 583 (Reconfigurable Computing): Course overview Serial UART Echo. vhd Iowa State University
Machine Problems (MPs) Agenda 1. Platform Introduction 2. Network String Matching 3. Image: PPC coprocessor FPGA 4. Final Projects(~6 weeks) PC 18 - ECp. E 583 (Reconfigurable Computing): Course overview Serial UART Echo. vhd (Modify to capitalize only (a-z)) Iowa State University
Machine Problems (MPs) Agenda 1. Platform Introduction 2. Network String Matching 3. Image: PPC coprocessor FPGA 4. Final Projects(~6 weeks) PC 19 - ECp. E 583 (Reconfigurable Computing): Course overview Ethernet (UDP/IP) Echo. vhd Iowa State University
Machine Problems (MPs) Agenda 1. Platform Introduction 2. Network String Matching 3. Image: PPC coprocessor FPGA 4. Final Projects(~6 weeks) PC 20 - ECp. E 583 (Reconfigurable Computing): Course overview Ethernet (UDP/IP) Echo. vhd (Modify to count strings (e. g. corn!)) Iowa State University
Machine Problems (MPs) Agenda 1. Platform Introduction FPGA 2. Network String Matching Power PC 3. Image: PPC coprocessor 4. Final Projects(~6 weeks) PC Ethernet (UDP/IP) Display. c User Defined Instruction Monitor 21 - ECp. E 583 (Reconfigurable Computing): Course overview VGA Iowa State University
Machine Problems (MPs) Agenda 1. Platform Introduction FPGA 2. Network String Matching Power PC 3. Image: PPC coprocessor 4. Final Projects(~6 weeks) PC Ethernet (UDP/IP) Display. c User Defined Instruction Monitor 22 - ECp. E 583 (Reconfigurable Computing): Course overview VGA Iowa State University
Machine Problems (MPs) Agenda 1. Platform Introduction FPGA 2. Network String Matching Power PC 3. Image: PPC coprocessor 4. Final Projects(~6 weeks) PC Ethernet (UDP/IP) Display. c User Defined Instruction Monitor 23 - ECp. E 583 (Reconfigurable Computing): Course overview VGA Iowa State University
Machine Problems (MPs) Agenda 1. Platform Introduction • Choose your own topic 2. Network String Matching 3. Image: PPC coprocessor 4. Final Projects(~6 weeks) • Groups of 3 -4 (maybe 5 for case by case) • Encouraged to take on aggressive projects 24 - ECp. E 583 (Reconfigurable Computing): Course overview Iowa State University
Review Syllabus • Objects • Expectations • Grading breakdown • MP grading policy: (more flexible for Distance Students) – Up to 5% added for early completion (Fri Midnight) – -5% after Fri Midnight – -10% additional after Monday Midnight – -10% additional after Tue Midnight – After Wed Midnight will make a note. 25 - ECp. E 583 (Reconfigurable Computing): Course overview Iowa State University
What is Reconfigurable Computing? • Ask wiki: http: //en. wikipedia. org/wiki/Reconfigurable_computing • Computing on a medium that is not fixed • Examples: – r. DPA (course grain reconfiguration) – FPGA (fine grain reconfiguration) – General Purpose Processor (not really) underlining hardware typical executes a relatively small fixed instruction set. 26 - ECp. E 583 (Reconfigurable Computing): Course overview Iowa State University
What are r. DPAs? • r. DPA: reconfigurable Data Path Array • Function Units with programmable interconnects Example ALU ALU ALU 27 - ECp. E 583 (Reconfigurable Computing): Course overview Iowa State University
What are r. DPAs? • r. DPA: reconfigurable Data Path Array • Function Units with programmable interconnects Example ALU ALU ALU 28 - ECp. E 583 (Reconfigurable Computing): Course overview Iowa State University
What are r. DPAs? • r. DPA: reconfigurable Data Path Array • Function Units with programmable interconnects Example ALU ALU ALU 29 - ECp. E 583 (Reconfigurable Computing): Course overview Iowa State University
What are FPGAs? • FPGA: Field Programmable Gate Array • Sea of general purpose logic gates CLB CLB CLB CLB 30 - ECp. E 583 (Reconfigurable Computing): Course overview Configurable Logic Block Iowa State University
What are FPGAs? • FPGA: Field Programmable Gate Array • Sea of general purpose logic gates CLB CLB CLB CLB 31 - ECp. E 583 (Reconfigurable Computing): Course overview Configurable Logic Block Iowa State University
What are FPGAs? • FPGA: Field Programmable Gate Array • Sea of general purpose logic gates CLB CLB Configurable Logic Block CLB CLB 32 - ECp. E 583 (Reconfigurable Computing): Course overview CLB Iowa State University
Some FPGA Details CLB CLB 33 - ECp. E 583 (Reconfigurable Computing): Course overview Iowa State University
Some FPGA Details CLB A B C D CLB Z CLB LUT 4 input Look Up Table ABCD Z 0000 0001 1110 1111 34 - ECp. E 583 (Reconfigurable Computing): Course overview Iowa State University
Some FPGA Details CLB A B C D CLB Z CLB LUT 4 input Look Up Table ABCD Z 0000 0 0001 0 1111 35 - ECp. E 583 (Reconfigurable Computing): Course overview 0 1 A B C D AND Z Iowa State University
Some FPGA Details CLB A B C D CLB Z CLB LUT 4 input Look Up Table ABCD Z 0000 0 0001 1 1110 1111 36 - ECp. E 583 (Reconfigurable Computing): Course overview 1 1 A B C D OR Z Iowa State University
Some FPGA Details CLB A B C D CLB Z CLB LUT 4 input Look Up Table ABCD Z X 000 0 X 001 1 X 110 X 111 37 - ECp. E 583 (Reconfigurable Computing): Course overview 1 1 B C D 2: 1 Z Mux Iowa State University
Some FPGA Details CLB A B C D CLB Z LUT 38 - ECp. E 583 (Reconfigurable Computing): Course overview CLB Iowa State University
Some FPGA Details CLB PIP Programmable Interconnection Point A B C D Z LUT DFF 39 - ECp. E 583 (Reconfigurable Computing): Course overview CLB Iowa State University
Some FPGA Details CLB PIP Programmable Interconnection Point A B C D Z LUT DFF 40 - ECp. E 583 (Reconfigurable Computing): Course overview CLB Iowa State University
FPGA Usage Models • Experimental ISA • Experimental Micro Architectures CPU + Specialized HW - Sparc-V 8 Leon Fast Prototyping System on Chip (So. C) Parallel Applications • Image Processing • Computational Biology 41 - ECp. E 583 (Reconfigurable Computing): Course overview • Run-time adaptation • Run-time Customization Partial Reconfiguration Full Reconfiguration • Remote Update • Fault Tolerance Iowa State University
Application Area for Acceleration 42 - ECp. E 583 (Reconfigurable Computing): Course overview Iowa State University
Development Platform Overview • ML 507 Evaluation Platform User Guide (pgs. 14 -16) – http: //www. xilinx. com/support/documentation/boards_and_kits/ug 347. pdf 43 - ECp. E 583 (Reconfigurable Computing): Course overview Iowa State University
Machine Problem 1 (MP 1) Short Overview • Assigned Fri (8/27), Due Friday (9/10). • Purpose: Make sure you can run the tools. Very light VHDL coding. • Primary Tasks: – Run the echo circuit without modifications – Run the echo circuit with a modification to convert lower case ASCII characters to upper case. • Distance Students: Test using NX for remotely access xilinx. ece. iastate. edu. You can download the NX client from: – – For Windows: http: //www. nomachine. com/download-client-windows. php For Linux: http: //www. nomachine. com/download-client-linux. php For MAC OS: http: //www. nomachine. com/download-client-macosx. php For Solaris: http: //www. nomachine. com/download-client-solaris. php 44 - ECp. E 583 (Reconfigurable Computing): Course overview Iowa State University
VHDL basics • VHDL: (V)HSIC (H)ardware (D)escription (L)anguage – VHSIC: (V)ery (H)igh (S)peed (I)ntegrated (C)ircuit • It is NOT a programming language!!! • It is a Hardware Description Language (HDL) • Conceptually VERY different form C, C++ • Some links to VHDL tutorials – http: //www. seas. upenn. edu/~ese 201/vhdl_primer. html – http: //www. vhdl-online. de/tutorial/ – http: //hapssupportnet. synplicity. com/download/VHDL-Handbook. pdf (quick ref) 45 - ECp. E 583 (Reconfigurable Computing): Course overview Iowa State University
Some Key Differences from C • C is inherently sequential (serial), one statement executed at a time • VHDL is inherently concurrent (parallel), many statements execute (simulate) at a time 46 - ECp. E 583 (Reconfigurable Computing): Course overview Iowa State University
Some Key Differences from C C example VHDL example Initially: A, B, C, X, Y, Z, Ans =1 A=B+C X=Y+Z Ans = A + X Current Values: A=1 B=1 C=1 X=1 Y=1 Z=1 Ans = 1 47 - ECp. E 583 (Reconfigurable Computing): Course overview A <= B + C X <= Y + Z Ans <= A + X Current Values: A=1 B=1 C=1 X=1 Y=1 Z=1 Ans = 1 Iowa State University
Some Key Differences from C C example VHDL example Initially: A, B, C, X, Y, Z, Ans =1 A=B+C X=Y+Z Ans = A + X Current Values: A=2 B=1 C=1 X=1 Y=1 Z=1 Ans = 1 48 - ECp. E 583 (Reconfigurable Computing): Course overview A <= B + C X <= Y + Z Ans <= A + X Current Values: A=1 B=1 C=1 X=1 Y=1 Z=1 Ans = 1 Iowa State University
Some Key Differences from C C example VHDL example Initially: A, B, C, X, Y, Z, Ans =1 A=B+C X=Y+Z Ans = A + X Current Values: A=2 B=1 C=1 X=2 Y=1 Z=1 Ans = 1 49 - ECp. E 583 (Reconfigurable Computing): Course overview A <= B + C X <= Y + Z Ans <= A + X Current Values: A=1 B=1 C=1 X=1 Y=1 Z=1 Ans = 1 Iowa State University
Some Key Differences from C C example VHDL example Initially: A, B, C, X, Y, Z, Ans =1 A=B+C X=Y+Z Ans = A + X Current Values: A=2 B=1 C=1 X=2 Y=1 Z=1 Ans = 4 50 - ECp. E 583 (Reconfigurable Computing): Course overview A <= B + C X <= Y + Z Ans <= A + X Current Values: A=1 B=1 C=1 X=1 Y=1 Z=1 Ans = 1 Iowa State University
Some Key Differences from C VHDL example C example Initially: A, B, C, X, Y, Z, Ans =1 A=B+C X=Y+Z Ans = A + X A <= B + C X <= Y + Z Ans <= A + X “Simulates in parallel ever delta time step” Current Values: A=2 B=1 C=1 X=2 Y=1 Z=1 Ans = 4 51 - ECp. E 583 (Reconfigurable Computing): Course overview Current Values: A=1 B=1 C=1 X=1 Y=1 Z=1 Ans = 1 Iowa State University
Some Key Differences from C VHDL example C example Initially: A, B, C, X, Y, Z, Ans =1 A=B+C X=Y+Z Ans = A + X Snap shot after input change A <= B + C X <= Y + Z Ans <= A + X “Simulates in parallel ever delta time step” Current Values: A=2 B=1 C=1 X=2 Y=1 Z=1 Ans = 4 52 - ECp. E 583 (Reconfigurable Computing): Course overview Current Values: A=1 B=1 C=1 X=1 Y=1 Z=1 Ans = 1 Iowa State University
Some Key Differences from C VHDL example C example Initially: A, B, C, X, Y, Z, Ans =1 A=B+C X=Y+Z Ans = A + X A <= B + C X <= Y + Z Ans <= A + X “Simulates in parallel ever delta time step” Current Values: A=2 B=1 C=1 X=2 Y=1 Z=1 Ans = 4 53 - ECp. E 583 (Reconfigurable Computing): Course overview Current Values: A=2 B=1 C=1 X=2 Y=1 Z=1 Ans = 2 Iowa State University
Some Key Differences from C VHDL example C example Initially: A, B, C, X, Y, Z, Ans =1 A=B+C X=Y+Z Ans = A + X A <= B + C X <= Y + Z Ans <= A + X “Simulates in parallel ever delta time step” Current Values: A=2 B=1 C=1 X=2 Y=1 Z=1 Ans = 4 Different 54 - ECp. E 583 (Reconfigurable Computing): Course overview Current Values: A=2 B=1 C=1 X=2 Y=1 Z=1 Ans = 2 Iowa State University
Some Key Differences from C VHDL example C example Initially: A, B, C, X, Y, Z, Ans =1 A=B+C X=Y+Z Ans = A + X Snap shot after input change A <= B + C X <= Y + Z Ans <= A + X “Simulates in parallel ever delta time step” Current Values: A=2 B=1 C=1 X=2 Y=1 Z=1 Ans = 4 55 - ECp. E 583 (Reconfigurable Computing): Course overview Current Values: A=2 B=1 C=1 X=2 Y=1 Z=1 Ans = 2 Iowa State University
Some Key Differences from C VHDL example C example Initially: A, B, C, X, Y, Z, Ans =1 A=B+C X=Y+Z Ans = A + X A <= B + C X <= Y + Z Ans <= A + X “Simulates in parallel ever delta time step” Current Values: A=2 B=1 C=1 X=2 Y=1 Z=1 Ans = 4 56 - ECp. E 583 (Reconfigurable Computing): Course overview Current Values: A=2 B=1 C=1 X=2 Y=1 Z=1 Ans = 2 Iowa State University
Some Key Differences from C VHDL example C example Initially: A, B, C, X, Y, Z, Ans =1 A=B+C X=Y+Z Ans = A + X A <= B + C X <= Y + Z Ans <= A + X “Simulates in parallel ever delta time step” Current Values: A=2 B=1 C=1 X=2 Y=1 Z=1 Ans = 4 57 - ECp. E 583 (Reconfigurable Computing): Course overview Current Values: A=2 B=1 C=1 X=2 Y=1 Z=1 Ans = 4 Iowa State University
Corresponding circuit VHDL example Initially: A, B, C, X, Y, Z, Ans =1 A <= B + C X <= Y + Z Ans <= A + X “Simulates in parallel ever delta time step” 58 - ECp. E 583 (Reconfigurable Computing): Course overview Iowa State University
Corresponding circuit VHDL example Initially: A, B, C, X, Y, Z, Ans =1 A <= B + C X <= Y + Z Ans <= A + X “Simulates in parallel ever delta time step” B(1) C(1) + A(1) + Y(1) Z(1) + 59 - ECp. E 583 (Reconfigurable Computing): Course overview Ans(1) X(1) Iowa State University
Corresponding circuit VHDL example Initially: A, B, C, X, Y, Z, Ans =1 A <= B + C X <= Y + Z Ans <= A + X “Simulates in parallel ever delta time step” B(1) C(1) + A(2) + Y(1) Z(1) + 60 - ECp. E 583 (Reconfigurable Computing): Course overview Ans(2) X(2) Iowa State University
Corresponding circuit VHDL example Initially: A, B, C, X, Y, Z, Ans =1 A <= B + C X <= Y + Z Ans <= A + X “Simulates in parallel ever delta time step” B(1) C(1) + A(2) + Y(1) Z(1) + 61 - ECp. E 583 (Reconfigurable Computing): Course overview Ans(4) X(2) Iowa State University
Corresponding circuit (More realistic) VHDL example Initially: A, B, C, X, Y, Z, Ans =1 A <= B + C after 2 ns X <= Y + Z after 2 ns Ans <= A + X after 2 ns “Simulates in parallel ever delta time step” B(1) C(1) Y(1) Z(1) + A(1) 2 ns + + X(1) Ans(1) 2 ns 62 - ECp. E 583 (Reconfigurable Computing): Course overview Iowa State University
Corresponding circuit (More realistic) VHDL example Initially: A, B, C, X, Y, Z, Ans =1 A <= B + C after 2 ns X <= Y + Z after 2 ns Ans <= A + X after 2 ns “Simulates in parallel ever delta time step” B(1) C(1) Y(1) Z(1) + A(2) 2 ns + + X(2) Ans(2) 2 ns 63 - ECp. E 583 (Reconfigurable Computing): Course overview Iowa State University
Corresponding circuit (More realistic) VHDL example Initially: A, B, C, X, Y, Z, Ans =1 A <= B + C after 2 ns X <= Y + Z after 2 ns Ans <= A + X after 2 ns “Simulates in parallel ever delta time step” B(1) C(1) Y(1) Z(1) + A(2) 2 ns + + X(2) Ans(4) 2 ns 64 - ECp. E 583 (Reconfigurable Computing): Course overview Iowa State University
Typical Structure of a VHDL File LIBRARY ieee; ENTITY test_circuit IS PORT(B, C, Y, Z, Ans); END test_circuit; Include Libraries Define component name and Input/output ports Declare internal ARCHITECTURE structure OF test_circuit IS signal A : std_logic_vector(7 downto 0); signals, signal X : std_logic_vector(7 downto 0); components BEGIN A <= B or C; Implement components functionality END 65 - ECp. E 583 (Reconfigurable Computing): Course overview Iowa State University
Next Lecture • Basic components of an FPGA • VHDL overview cont. 66 - ECp. E 583 (Reconfigurable Computing): Course overview Iowa State University
Questions/Comments/Concerns 67 - ECp. E 583 (Reconfigurable Computing): Course overview Iowa State University
Fast Prototyping System on Chip (So. C) Parallel Applications 68 - ECp. E 583 (Reconfigurable Computing): Course overview Partial Reconfiguration Full Reconfiguration Iowa State University
Highly Parallel Applications Fast Prototyping System on Chip (So. C) Parallel Applications 69 - ECp. E 583 (Reconfigurable Computing): Course overview Partial Reconfiguration Full Reconfiguration Iowa State University
System on Chip (So. C) Fast Prototyping System on Chip (So. C) Parallel Applications 70 - ECp. E 583 (Reconfigurable Computing): Course overview Partial Reconfiguration Full Reconfiguration Iowa State University
Full Reconfiguration Fast Prototyping System on Chip (So. C) Parallel Applications 71 - ECp. E 583 (Reconfigurable Computing): Course overview Partial Reconfiguration Full Reconfiguration Iowa State University
Partial Reconfiguration Fast Prototyping System on Chip (So. C) Parallel Applications 72 - ECp. E 583 (Reconfigurable Computing): Course overview Partial Reconfiguration Full Reconfiguration Iowa State University
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