Cpr E 281 Digital Logic Instructor Alexander Stoytchev
- Slides: 87
Cpr. E 281: Digital Logic Instructor: Alexander Stoytchev http: //www. ece. iastate. edu/~alexs/classes/
Decoders and Encoders Cpr. E 281: Digital Logic Iowa State University, Ames, IA Copyright © Alexander Stoytchev
Administrative Stuff • HW 7 is out • It is due next Monday (March 10)
Administrative Stuff • Midterm Grades are Dues this Friday • only grades of C-, D, F have to be submitted to the registrar’s office
Quick Review
Graphical Symbol for a 2 -1 Multiplexer s x 1 0 x 2 1 f [ Figure 2. 33 c from the textbook ]
Circuit for 2 -1 Multiplexer x 1 s f s x 2 (b) Circuit x 1 0 x 2 1 f (c) Graphical symbol f (s, x 1, x 2) = s x 1 + s x 2 [ Figure 2. 33 b-c from the textbook ]
4 -to-1 Multiplexer: Graphical Symbol and Truth Table [ Figure 4. 2 a-b from the textbook ]
Using three 2 -to-1 multiplexers to build one 4 -to-1 multiplexer s 1 s 0 w 0 0 w 1 1 0 1 w 2 0 w 3 1 f [ Figure 4. 3 from the textbook ]
16 -1 Multiplexer s 0 s 1 w 0 w 3 w 4 s 2 s 3 w 7 f w 8 w 11 w 12 w 15 [ Figure 4. 4 from the textbook ]
Synthesis of Logic Circuits Using Multiplexers
Implementation of a logic function with a 4 x 1 multiplexer w 1 w 2 f 0 0 1 1 1 0 w 2 w 1 0 1 1 0 f [ Figure 4. 6 a from the textbook ]
Implementation of the same logic function with a 2 x 1 multiplexer w 1 w 2 f 0 0 1 1 1 0 (b) Modified truth table w 1 f 0 w 2 1 w 2 w 1 w 2 f (c) Circuit [ Figure 4. 6 b-c from the textbook ]
The XOR Logic Gate [ Figure 2. 11 from the textbook ]
The XOR Logic Gate [ Figure 2. 11 from the textbook ]
The XOR Logic Gate Implemented with a multiplexer f
The XOR Logic Gate Implemented with a multiplexer x f y
The XOR Logic Gate Implemented with a multiplexer x f y These two circuits are equivalent (the wires of the bottom and gate are flipped)
In other words, all four of these are equivalent! x y f x f y w 2 w 1 x y f 0 1 1 0 f
Another Example (3 -input XOR)
Implementation of 3 -input XOR with 2 -to-1 Multiplexers w 1 w 2 w 3 0 0 1 1 0 1 0 1 f 0 1 1 0 0 1 [ Figure 4. 8 a from the textbook ]
Implementation of 3 -input XOR with 2 -to-1 Multiplexers w 1 w 2 w 3 0 0 1 1 0 1 0 1 f 0 1 1 0 0 1 w 2 Å w 3 [ Figure 4. 8 a from the textbook ]
Implementation of 3 -input XOR with 2 -to-1 Multiplexers w 1 w 2 w 3 0 0 1 1 0 1 0 1 f 0 1 1 0 0 1 w 2 Å w 3 w 1 w 3 f w 2 Å w 3 (a) Truth table (b) Circuit [ Figure 4. 8 from the textbook ]
Implementation of 3 -input XOR with a 4 -to-1 Multiplexer w 1 w 2 w 3 0 0 1 1 0 1 0 1 f 0 1 1 0 0 1 [ Figure 4. 9 a from the textbook ]
Implementation of 3 -input XOR with a 4 -to-1 Multiplexer w 1 w 2 w 3 0 0 1 1 0 1 0 1 f 0 1 1 0 0 1 w 3 w 3 [ Figure 4. 9 a from the textbook ]
Implementation of 3 -input XOR with a 4 -to-1 Multiplexer w 1 w 2 w 3 0 0 1 1 0 1 0 1 f 0 1 1 0 0 1 w 3 w 2 w 1 w 3 f w 3 (a) Truth table (b) Circuit [ Figure 4. 9 from the textbook ]
Multiplexor Synthesis Using Shannon’s Expansion
Three-input majority function w 1 w 2 w 3 0 0 1 1 0 1 0 1 f 0 0 0 1 1 1 [ Figure 4. 10 a from the textbook ]
Three-input majority function w 1 w 2 w 3 0 0 1 1 0 1 0 1 f 0 0 0 1 1 1 w 1 f 0 1 [ Figure 4. 10 a from the textbook ]
Three-input majority function w 1 w 2 w 3 0 0 1 1 0 1 0 1 f 0 0 0 1 1 1 w 1 f 0 1 w 2 w 3 w 2 + w 3 [ Figure 4. 10 a from the textbook ]
Three-input majority function w 1 w 2 w 3 0 0 1 1 0 1 0 1 f 0 0 0 1 1 1 w 1 f 0 1 w 2 w 3 w 2 + w 3 (b) Truth table w 1 w 2 w 3 f (b) Circuit [ Figure 4. 10 from the textbook ]
Three-input majority function w 2 w 3 w 1 f
Shannon’s Expansion Theorem Any Boolean function can be rewritten in the form:
Shannon’s Expansion Theorem Any Boolean function can be rewritten in the form:
Shannon’s Expansion Theorem Any Boolean function can be rewritten in the form: cofactor
Shannon’s Expansion Theorem (Example)
Shannon’s Expansion Theorem (Example) (w 1 + w 1)
Shannon’s Expansion Theorem (Example) (w 1 + w 1)
Shannon’s Expansion Theorem (In terms of more than one variable) This form is suitable for implementation with a 4 x 1 multiplexer.
Another Example
Factor and implement the following function with a 2 x 1 multiplexer
Factor and implement the following function with a 2 x 1 multiplexer
Factor and implement the following function with a 2 x 1 multiplexer f w [ Figure 4. 11 a from the textbook ]
Factor and implement the following function with a 4 x 1 multiplexer
Factor and implement the following function with a 4 x 1 multiplexer
Factor and implement the following function with a 4 x 1 multiplexer [ Figure 4. 11 b from the textbook ]
Yet Another Example
Factor and implement the following function using only 2 x 1 multiplexers
Factor and implement the following function using only 2 x 1 multiplexers
Factor and implement the following function using only 2 x 1 multiplexers
Factor and implement the following function using only 2 x 1 multiplexers w 1 g h f
Factor and implement the following function using only 2 x 1 multiplexers
Factor and implement the following function using only 2 x 1 multiplexers
Factor and implement the following function using only 2 x 1 multiplexers w 2 0 w 3 w 2 g w 3 1 h
Finally, we are ready to draw the circuit w 2 0 w 1 g w 3 g h w 2 w 3 1 h f
Finally, we are ready to draw the circuit w 2 0 g w 1 w 3 f 1 h
Finally, we are ready to draw the circuit w 2 w 1 0 w 3 f 1 [ Figure 4. 12 from the textbook ]
Decoders
2 -to-4 Decoder (Definition) • Has two inputs: w 1 and w 0 • Has four outputs: y 0 , y 1 , y 2 , and y 3 • • If w 1=0 and w 0=0, then the output y 0 is set to 1 If w 1=0 and w 0=1, then the output y 1 is set to 1 If w 1=1 and w 0=0, then the output y 2 is set to 1 If w 1=1 and w 0=1, then the output y 3 is set to 1 • Only one output is set to 1. All others are set to 0.
Truth Table and Graphical Symbol for a 2 -to-4 Decoder [ Figure 4. 13 a-b from the textbook ]
Truth Logic Circuit for a 2 -to-4 Decoder [ Figure 4. 13 c from the textbook ]
Adding an Enable Input [ Figure 4. 13 c from the textbook ]
Adding an Enable Input En [ Figure 4. 13 c from the textbook ]
Truth Table and Graphical Symbol for a 2 -to-4 Decoder with an Enable Input [ Figure 4. 14 a-b from the textbook ]
Truth Table and Graphical Symbol for a 2 -to-4 Decoder with an Enable Input x indicates that it does not matter what the value of these variable is for this row of the truth table [ Figure 4. 14 a-b from the textbook ]
Graphical Symbol for a Binary n-to-2 n Decoder with an Enable Input A binary decoder with n inputs has 2 n outputs The outputs of an enabled binary decoder are “one-hot” encoded, meaning that only a single bit is set to 1, i. e. , it is hot. [ Figure 4. 14 d from the textbook ]
How can we build larger decoders? • 3 -to-8 ? • 4 -to-16? • 5 -to-? ?
Hint: How did we build a 16 -1 Multiplexer s 0 s 1 w 0 w 3 w 4 s 2 s 3 w 7 f w 8 w 11 w 12 w 15 [ Figure 4. 4 from the textbook ]
A 3 -to-8 decoder using two 2 -to-4 decoders w 0 w 1 w 2 En w 0 w 1 En y 0 y 1 y 2 y 3 y 4 y 5 y 6 y 7 [ Figure 4. 15 from the textbook ]
A 3 -to-8 decoder using two 2 -to-4 decoders w 0 w 1 w 2 En w 0 w 1 En En y 0 y 1 y 2 y 3 y 4 y 5 y 6 y 7 What is this? [ Figure 4. 15 from the textbook ]
What is this? w 0 y 0 En y 1
A 4 -to-16 decoder built using a decoder tree w 0 w 1 En w 0 w 1 w 2 w 3 w 0 w 1 En En y 0 y 1 y 2 y 3 En w 0 w 1 [ Figure 4. 16 from the textbook ] En y 0 y 1 y 2 y 3 y 4 y 5 y 6 y 7 y 0 y 1 y 2 y 3 y 8 y 9 y 10 y 11 y 0 y 1 y 2 y 3 y 12 y 13 y 14 y 15
Let’s build a 5 -to-32 decoder
Demultiplexers
1 -to-4 Demultiplexer (Definition) • Has one data input line: D • Has two output select lines: w 1 and w 0 • Has four outputs: y 0 , y 1 , y 2 , and y 3 • • If w 1=0 and w 0=0, then the output y 0 is set to D If w 1=0 and w 0=1, then the output y 1 is set to D If w 1=1 and w 0=0, then the output y 2 is set to D If w 1=1 and w 0=1, then the output y 3 is set to D • Only one output is set to D. All others are set to 0.
A 1 -to-4 demultiplexer built with a 2 -to-4 decoder [ Figure 4. 14 c from the textbook ]
A 1 -to-4 demultiplexer built with a 2 -to-4 decoder output select lines the four output lines data input line D [ Figure 4. 14 c from the textbook ]
Multiplexers (Implemented with Decoders)
A 4 -to-1 multiplexer built using a 2 -to-4 decoder w 0 w 1 s 0 s 1 1 w 0 w 1 En y 0 y 1 y 2 y 3 f w 2 w 3 [ Figure 4. 17 from the textbook ]
Encoders
Binary Encoders
A 2 n-to-n binary encoder w 0 2 n inputs w 2 n – 1 y 0 yn – 1 n outputs [ Figure 4. 18 from the textbook ]
A 4 -to-2 binary encoder w 3 w 2 w 1 w 0 0 1 0 0 0 y 1 y 0 0 0 1 1 0 1 (a) Truth table w 0 w 1 y 0 w 2 y 1 w 3 (b) Circuit [ Figure 4. 19 from the textbook ]
Priority Encoders
Truth table for a 4 -to-2 priority encoder w 3 w 2 w 1 w 0 0 0 1 x x 0 1 x x x y 1 y 0 z d 0 0 1 1 1 1 d 0 1 [ Figure 4. 20 from the textbook ]
Questions?
THE END
- Stoytchev 281
- Stoytchev 281
- Cpr e 281
- Stoytchev
- What is this
- Ipx 281
- Cs 281 wordpress
- Geo 281
- Geo 281
- Cbhs seniors
- Cs 281
- Numeros romanos del 400 al 600
- Dönem ayirici hesaplar 180 181 280 281 380 381
- Dönem ayirici hesaplar 180 181 280 281 380 381
- First order logic vs propositional logic
- First order logic vs propositional logic
- Third order logic
- Concurrent vs sequential
- Tw
- Project management plan example
- Majority circuit
- Combinational logic sequential logic 차이
- Logic chapter three
- Digital logic design tutorial
- Is a multiplexer a state machine
- Timing diagram for nand gate
- Digital logic design number system
- Plc mixer process control problem
- Canonical form digital logic
- Digital logic design practice problems
- Digital logic
- Digital logic design lectures
- Digital logic structures
- The boolean expression
- Bubble matching digital logic
- Digital logic and computer architecture
- Uncommon logic digital
- Digital design review
- Duality in discrete mathematics
- Digital logic design
- Bubble matching digital logic
- Tipos de participantes en un curso
- Basic instructor course texas
- Basic instructor course texas
- Basic instructor course texas
- Pepperball training manual
- Neither of my two suitcases are adequate for this trip
- Instructor vs teacher
- Ospfv
- Mptc firearms instructor manual
- Tcole advanced instructor course
- Basic instructor course texas
- Virtual art instructor
- Nfpa 1403 instructor to student ratio
- Tp 12863
- Instructor operating station
- Catia instructor
- Instructor
- Instructor responsibilities and professionalism lesson plan
- Tcole 1014 basic instructor course
- Usmc jrotc vacancies
- How to become an nrp instructor mentor
- Utp cable
- What is cbrf training
- Nra certified instructor logo
- Naismith was an instructor of
- Please clean your room
- Tcole advanced instructor course
- Tcole advanced instructor course
- Jrotc marksmanship instructor course online
- Forced perspective room
- Acr medical term
- Basic instructor course #1014
- Basic instructor course tcole
- Delmar cengage learning instructor resources
- Instructor office hours
- Extracorporeal cpr
- Kedudukan pemulihan cpr
- Perbedaan cpr dan mpr
- Infant cpr algorithm
- High quality cpr infant
- Objectives of cpr
- Secondary survey cpr
- Llf in first aid
- Ems safety cpr
- Emotional cpr training
- Cpr hand placement sternum
- Cpr for beginners