CPEEE 421 Microcomputers Motorola 68000 Architecture Assembly Programming

CPE/EE 421 Microcomputers: Motorola 68000: Architecture & Assembly Programming Instructor: Dr Aleksandar Milenkovic Lecture Notes CPE/EE 421/521 Microcomputers

Outline n n Programmer’s Model Assembly Language Directives Addressing Modes Instruction Set CPE/EE 421/521 Microcomputers 2

Motorola 68000 n n CISC processor sixteen 32 -bit registers n n n eight general purpose data registers eight general purpose address registers User/supervisor space 64 -pin package Clock 8 MHz, 12. 5 MHz CPE/EE 421/521 Microcomputers 3

Programming Model of the 68000* n n n *Registers, Addressing Modes, Instruction Set NOTE: The 68000 architecture forms a subset of the 68020’s architecture (i. e. , 68020 is backward compatible) NOTE: n n D 31 – subscripted 2 digits mean bit location D 0 – unsubscripted one digit means register name e s o p r pu rs l era iste n Ge reg rs e t is g re r e t in o P CPE/EE 421/521 Microcomputers 4

Memory Organization Figure 2. 4 Long word address = Address of the high order 16 bits of the longword Big-Endian – The most significant unit is stored at the lowest address CPE/EE 421/521 Microcomputers 5

Special Purpose Registers Status Register PC – Program Counter: Outcome of ALU operation 32 bits, contains the address of the next instruction to be executed ADD. B D 0, D 1 78 DF 157 Figure 2. 5 Carry CPE/EE 421/521 Microcomputers 6

The Bits of the MC 68000 Status Register CPE/EE 421/521 Microcomputers 7

C, V and X Bits of Status Register ADD. B 40 +70 78 +DF B 0 57 Carry 1011 0000 157 sign C - set int a; char b; a=(int)b; X - extend V - set … 1111 10110000 CPE/EE 421/521 Microcomputers 8

Outline n n Programmer’s Model Assembly Language Directives Addressing Modes Instruction Set CPE/EE 421/521 Microcomputers 9

Assembly Language Programming n Machine code/Assembly language n n A form of the native language of a computer Development environment Assembly program structure Assembly directives CPE/EE 421/521 Microcomputers 10

Assembly Language Programming ASSEMBLER SOURCE FILE fname. x 68 MACHINE CODE OBJECT LISTING FILE LINKER/LOADER COMPUTER MEMORY ASSEMBLY LANGUAGE: Symbolic representation of the native language of the computer MACHINE INSTRUCTIONS MNEMONICS ADDRESSES & CONSTANTS SYMBOLS CPE/EE 421/521 Microcomputers 11

Assembly Language Program: Example BACK-SP DELETE CAR-RET EQU $08 ASCII code for backspace EQU $01 ASCII code for delete EQU $OD ASCII code for carriage return ORG $004000 Data origin LINE-BUF DS. B 64 Reserve 64 bytes for line buffer * $ represents HEX * This procedure inputs a character and stores it in a buffer % represents BIN ORG $001000 Program origin LEA LINE-BUF, A 2 points to line buffer NEXT BSR GET_DATA Call subroutine to get input CMP. B #BACK_SP, D 0 Test for backspace BEQ MOVE_LFT If backspace then deal with it # indicates a CMP. B #DELETE Test for delete literal or BEQ CANCEL If delete then deal with it CMP. B #CAR-RET Test for carriage return immediate value BEQ EXIT If carriage return then exit (i. e. not an MOVE. B DO, (A 2)+ Else store input in memory address) BRA NEXT Repeat . . Remainder of program END $001000 LABEL FIELD INSTRUCTION FIELD COMMENT FIELD CPE/EE 421/521 Microcomputers 12

Assembly Language Program n 3 fields associated with each line: n LABELS n n n INSTRUCTION n n n Start in the first column of a line Refers to the address of the line it labels Must be 8 or less characters Start with a non-number Mnemonic (op code) and 0 or more parameters (operands) Parameters separated by commas COMMENTS n n Can appear after instruction (many assemblers require a ; or ‘) Can also be used in label field CPE/EE 421/521 Microcomputers 13

Assembly Language Program (cont’d) n Macroassembler n n A MACRO: a unit of inline code that is given a name by the programmer Example: n n n Instruction to push data on the stack: MOVE. W D 0, -(A 7) Define the macro: PUSH D 0 to replace it Can define a macro for more than one instruction CPE/EE 421/521 Microcomputers 14

Assembler Directives n n n EQU – The equate directive DC – The define a constant directive DS – The define a storage directive ORG – The origin directive END – The end directive CPE/EE 421/521 Microcomputers 15

The DC Directive First Date ORG DC. B DC. L $001000 10, 66 $0 A 1234 'April 8 1985‘ 1, 2 address Start of data region The values 10 and 66 are stored in consecutive bytes The value $000 A 1234 is stored as a longword The ASCII characters as stored as a sequence of 12 bytes Two longwords are set up with the values 1 and 2 Mem. contents 001000 0 A 42 001002 00 0 A 001004 12 34 001006 41 70 001008 72 69 00100 A 6 C 20 00100 C 38 20 00100 E 31 39 001010 38 35 001012 00 00 001014 00 01 001016 00 00 001018 00 02 00101 A DC. B 10, 66 DC. L $0 A 1234 DC. B ‘April 8 1985’ DC. L 1, 2 CPE/EE 421/521 Microcomputers 16

The DC Directive (cont’d) Assembler listing 1 2 3 4 00001000 00001002 00001006 1 00001012 5 n 0 A 42 000 A 1234 417072696 C 20 000000010000 0002 ORG FIRST: DC. B DC. L DATE: DC. B 382031393835 DC. L $001000 10, 66 $0 A 1234 ‘April 8 1985’ 1, 2 DC – define a constant n n n NOTE: Assemblers automatically align word and longword constants on a word boundary . B, . W, . L – specify 8, 16, or 32 -bit constants Normally preceded by a label to enable referring Prefix: n n n Decimal $ - Hexadecimal % - Binary CPE/EE 421/521 Microcomputers 17

DS – The Define Storage Directive n n Reserves the specified amount of storage Label DS. <size> <operand>. B, . W, or. L List 1 Array 4 Pointer VOLTS TABLE n n n DS. B DSLB DS. W 4 $80 16 1 256 Reserve 4 Reserve 128 Reserve 16 Reserve 1 Reserve 256 Number of elements bytes of memory longwords (64 bytes) word (2 bytes) words Unlike DC does not initialize the values Useful to reserve areas of memory that will be used during run time Label is set to equal the first address of storage CPE/EE 421/521 Microcomputers 18

ORG – The Origin Assembler Directive n n Defines the value of the location counter Absolute value ORG <operand> of the origin ORG $001000 Origin for data TABLE DS. W 256 Save 256 words for "TABLE" POINTER 1 POINTER 2 VECTOR_1 INIT SETUP 1 SETUP 2 ACIAC RDRF PIA DS. L DC. W EQU EQU EQU 1 1 1 0, $FFFF $03 $55 $008000 0 ACIAC+4 Save one longword for "POINTER 1" Save one longword for "POINTER 2" Save one longword for "VECTOR_1" Store two constants ($0000, $FFFF) Equate "SETUP 1" to the value 3 Equate "SETUP 2" to the value $55 Equate "ACIAC" to the value $8000 RDRF = Receiver Data Register Full Equate "PIA" to the value $8004 CPE/EE 421/521 Microcomputers 19

ORG $001000 Origin for data TABLE DS. W 256 Save 256 words for "TABLE" POINTER 1 POINTER 2 VECTOR_1 INIT SETUP 1 SETUP 2 ACIAC RDRF PIA DS. L DC. W EQU EQU EQU 1 1 1 0, $FFFF $03 $55 $008000 0 ACIAC+4 Save one longword for "POINTER 1" Save one longword for "POINTER 2" Save one longword for "VECTOR_1" Store two constants ($0000, $FFFF) Equate "SETUP 1" to the value 3 Equate "SETUP 2" to the value $55 Equate "ACIAC" to the value $8000 RDRF = Receiver Data Register Full Equate "PIA" to the value $8004 ENTRY GET_DATA 001210 (free) Assembler Directives: Example ORG $018000 Origin for program LEA ACIAC, A 0 A 0 points to the ACIA MOVE. B #SETUP 2, (A 0) Write initialization constant into ACIA BTST. B #RDRF, (A 0) Any data received? BNE GET_DATA Repeat until data ready MOVE. B 2(A 0), D 0 Read data from ACIA END $001000 CPE/EE 421/521 Microcomputers 20

Assembler Directives: Example CPE/EE 421/521 Microcomputers 21

Outline n n Programmer’s Model Assembly Language Directives Addressing Modes Instruction Set CPE/EE 421/521 Microcomputers 22

Addressing Modes Addressing modes are concerned with how the CPU accesses the operands used by its instructions CPE/EE 421/521 Microcomputers 23

Register Transfer Language (RTL) n n n Unambiguous notation to describe information manipulation Registers are denoted by their names (eg. D 1 -D 7, A 0 -A 7) Square brackets mean “the contents of” Base number noted by a prefix (%-binary, $-hex) Backward arrow indicates a transfer of information ( ) [D 4] 50 Put 50 into register D 4 [D 4] $1234 Put $1234 into register D 4 [D 3] $FE 1234 Put $FE 1234 into register D 3 CPE/EE 421/521 Microcomputers 24

Register Transfer Language (RTL) ADD <source>, <destination> [destination] [source] + [destination] MOVE <source>, <destination> [destination] [source] CPE/EE 421/521 Microcomputers 25

Register Direct Addressing Register direct addressing is the simplest addressing mode in which the source or destination of an operand is a data register or an address register. The contents of the specified source register provide the source operand. Similarly, if a register is a destination operand, it is loaded with the value specified by the instruction. The following examples all use register direct addressing for source and destination operands. MOVE. B SUB. L CMP. W ADD D 0, D 3 A 0, D 3 D 2, D 0 D 3, D 4 D 3[0: 7] <- D 0[0: 7] Subtract the source operand in register A 0 from register D 3 Compare the source operand in register D 2 with register D 0 Add the source operand in register D 3 to register D 4 CPE/EE 421/521 Microcomputers 26

Register Direct Addressing The instruction indicates the data register The source operand is data register D 0 D 1 The MOVE. B D 0, D 1 instruction uses data registers for both source and destination operands CPE/EE 421/521 Microcomputers 27

Register Direct Addressing D 0 D 1 The destination operand is data register D 1 CPE/EE 421/521 Microcomputers 28

Register Direct Addressing D 0 D 1 The effect of this instruction is TO COPY the contents of data register D 0 in to data register D 1 CPE/EE 421/521 Microcomputers 29

Register Direct Addressing n n n Register direct addressing uses short instructions because it takes only three bits to specify one of eight data registers. Register direct addressing is fast because the external memory does not have to be accessed. Programmers use register direct addressing to hold variables that are frequently accessed (i. e. , scratchpad storage). CPE/EE 421/521 Microcomputers 30

Immediate Addressing n n n In immediate addressing the actual operand forms part of the instruction. An immediate operand is also called a literal operand. Immediate addressing can be used only to specify a source operand. Immediate addressing is indicated by a # symbol in front of the source operand. For example, MOVE. B #24, D 0 uses the immediate source operand 24. CPE/EE 421/521 Microcomputers 31

Immediate Addressing D 0 The instruction MOVE. B #4, D 0 uses a literal source operand a register direct destination operand CPE/EE 421/521 Microcomputers 32

Immediate Addressing The literal source operand, 4, is part of the instruction D 0 CPE/EE 421/521 Microcomputers 33

Immediate Addressing D 0 The destination operand is a data register CPE/EE 421/521 Microcomputers 34

Immediate Addressing D 0 The effect of this instruction is to copy the literal value 4 to data register D 0 CPE/EE 421/521 Microcomputers 35

Immediate Addressing Example n Typical application is in setting up control loops: for(i=0; i<128; i++) A(i) = 0 x. FF; n 68000 assembly language implementation: MOVE. L #$001000, A 0 Load A 0 with the address of the array MOVE. B #128, D 0 is the element counter LOOP MOVE. B #$FF, (A 0)+ Store $FF in this elem. and incr. pointer SUBQ. B #1, D 0 Decrement element counter BNE LOOP Repeat until all the elements are set CPE/EE 421/521 Microcomputers 36

Direct (or Absolute) Addressing n n n In direct or absolute addressing, the instruction provides the address of the operand in memory. Direct addressing requires two memory accesses. The first is to access the instruction and the second is to access the actual operand. For example, CLR. B 1234 clears the contents of memory location 1234. CPE/EE 421/521 Microcomputers 37

Direct (or Absolute) Addressing Memory M OV E. B 2 0 , D 0 20 This instruction has a direct source operand 42 D 0 The source operand is in memory The destination operand uses data register direct addressing CPE/EE 421/521 Microcomputers 38

Direct (or Absolute) Addressing Memory M OV E. B 2 0 , D 0 The address of the operand forms part of the instruction This is the actual operand 20 42 D 0 Once the CPU has read the operand address from the instruction, the CPU accesses the actual operand CPE/EE 421/521 Microcomputers 39

Direct (or Absolute) Addressing Memory M OV E. B 2 0 , D 0 20 42 42 D 0 The effect of MOVE. B 20, D 0 is to read the contents of memory location 20 and copy them to D 0 CPE/EE 421/521 Microcomputers 40

An Example D 0 [M(1001)] + D 0 A = Y + A Instruction: 1000 1002 ADD Y, D 0 3 9 1 1 0 0 0 0 1 1 1 0 0 1 Instruction ADD Reg. D 0 Size Source Destination BYTE addressing EA=next 2 words Effective Address : 0000 Register D 1001 CPE/EE 421/521 Microcomputers 41

An Example Assembler: PC ADD. B Y, D 0 3 9 0 0 Instructions ADD Y, D 0 1 0 0 1 Y (DATA) 1000 1002 Instruction : D 039 Effective Address : 0 0 CPE/EE 421/521 Microcomputers 1001 42

Summary of Fundamental Addressing Modes n n Consider the high-level language example: Z=Y+4 The following fragment of code implements this construct Y Z ORG MOVE. B ADD MOVE. B $400 Y, D 0 #4, D 0, Z Start of code ORG DC. B DS. B $600 27 1 Start of data area Store the constant 27 in memory Reserve a byte for Z CPE/EE 421/521 Microcomputers 43

The Assembled Program 1 2 3 4 5 6 7 8 9 10 00000400 00000406 0000040 A 00000410 1039000006000018 13 C 000000601 4 E 722700 ORG MOVE. B ADD. B MOVE. B STOP $400 Y, D 0 #24, D 0, Z #$2700 ORG DC. B DS. B END $600 27 1 $400 * 00000600 1 B 00000601 00000001 00000400 Y: Z: CPE/EE 421/521 Microcomputers 44

Memory Map of the Program Memory (numeric form) Y is a variable accessed via the direct address 000600 Memory (mnemonic form) 000400 103900000600 MOVE. B Y, D 0 000406 06000018 ADD. B #24, D 0 00040 A 13 C 000000601 MOVE. B D 0, Z 000410 4 E 722700 STOP #$2700 000600 1 B Y 000601 1 Z 27 Z is a variable accessed via the direct address 000601 This is a literal operand stored as part of the instruction CPE/EE 421/521 Microcomputers 45

Summary n n Register direct addressing is used for variables that can be held in registers Literal (immediate) addressing is used for constants that do not change Direct (absolute) addressing is used for variables that reside in memory The only difference between register direct addressing and direct addressing is that the former uses registers to store operands and the latter uses memory CPE/EE 421/521 Microcomputers 46

Address Register Indirect Addressing n n n In address register indirect addressing, the instruction specifies one of the 68000’s address registers; for example, MOVE. B (A 0), D 0. The specified address register contains the address of the operand. The processor then accesses the operand pointed at by the address register. CPE/EE 421/521 Microcomputers 47

Address Register Indirect Addressing RTL Form: [D 0] [M([A 0])] Memory A 0 MOVE. B (A 0), D 0 1000 This instruction means load D 0 with the contents of the location pointed at by address register A 0 42 1000 D 0 The instruction specifies the source operand as (A 0). CPE/EE 421/521 Microcomputers 48

Address Register Indirect Addressing RTL Form: [D 0] [M([A 0])] Memory MOVE. B (A 0), D 0 A 0 1000 57 D 0 The address register in the instruction specifies an address register that holds the address of the operand CPE/EE 421/521 Microcomputers 49

Address Register Indirect Addressing RTL Form: [D 0] [M([A 0])] Memory MOVE. B (A 0), D 0 A 0 1000 57 D 0 The address register is used to access the operand in memory CPE/EE 421/521 Microcomputers 50

Address Register Indirect Addressing RTL Form: [D 0] [M([A 0])] Memory A 0 MOVE. B (A 0), D 0 1000 57 D 0 Finally, the contents of the address register pointed at by A 0 are copied to the data register CPE/EE 421/521 Microcomputers 51

Auto-incrementing If the addressing mode is specified as (A 0)+, the contents of the address register are incremented after they have been used. CPE/EE 421/521 Microcomputers 52

Auto-incrementing Memory A 0 MOVE. B (A 0)+, D 0 1000 57 D 0 The address register contains 1000 and points at location 1000 CPE/EE 421/521 Microcomputers 53

Auto-incrementing Memory MOVE. B (A 0)+, D 0 A 0 1000 57 D 0 1001 Address register A 0 is used to access memory location 1000 and the contents of this location (i. e. , 57) are added to D 0 CPE/EE 421/521 Microcomputers 54

Auto-incrementing Memory A 0 MOVE. B (A 0)+, D 0 1001 1000 1001 D 0 43 After the instruction has been executed, the contents of A 0 are incremented to point at the next location CPE/EE 421/521 Microcomputers 55

Use of Address Register Indirect Addressing The following fragment of code uses address register indirect addressing with post-incrementing to add together five numbers stored in consecutive memory locations. Loop MOVE. B LEA CLR. B ADD. B SUB. B BNE STOP * Table DC. B #5, D 0 Table, A 0 D 1 (A 0)+, D 1 #1, D 0 Loop #$2700 Five numbers to add A 0 points at the numbers Clear the sum REPEAT Add number to total 1, 4, 2, 6, 5 Some dummy data UNTIL all numbers added We are now going to trace through part of this program, instruction by instruction. CPE/EE 421/521 Microcomputers 56

Use of Address Register Indirect Addressing >DF PC=000400 SR=2000 SS=00 A 00000 US=0000 A 0=0000 A 1=0000 A 2=0000 A 3=0000 A 4=0000 A 5=0000 A 6=0000 A 7=00 A 00000 D 0=0000 D 1=0000 D 2=0000 D 3=0000 D 4=0000 D 5=0000 D 6=0000 D 7=0000 ----->MOVE. B #$05, D 0 X=0 N=0 Z=0 V=0 C=0 >TR PC=000404 SR=2000 SS=00 A 00000 US=0000 A 0=0000 A 1=0000 A 2=0000 A 3=0000 A 4=0000 A 5=0000 A 6=0000 A 7=00 A 00000 D 0=00000005 D 1=0000 D 2=0000 D 3=0000 D 4=0000 D 5=0000 D 6=0000 D 7=0000 ----->LEA. L $0416, A 0 X=0 N=0 Z=0 V=0 C=0 Trace> PC=00040 A SR=2000 SS=00 A 00000 US=0000 A 0=00000416 A 1=0000 A 2=0000 A 3=0000 A 4=0000 A 5=0000 A 6=0000 A 7=00 A 00000 D 0=00000005 D 1=0000 D 2=0000 D 3=0000 D 4=0000 D 5=0000 D 6=0000 D 7=0000 ----->CLR. B D 1 X=0 N=0 Z=0 V=0 CPE/EE 421/521 Microcomputers The first instruction loads D 0 with the literal value 5 D 0 has been loaded with 5 This instruction loads A 0 with the value $0416 A 0 contains $0416 57

Use of Address Register Indirect Addressing Trace> PC=00040 C SR=2004 SS=00 A 00000 US=0000 A 0=00000416 A 1=0000 A 2=0000 A 3=0000 A 4=0000 A 5=0000 A 6=0000 A 7=00 A 00000 D 0=00000005 D 1=0000 D 2=0000 D 3=0000 D 4=0000 D 5=0000 D 6=0000 D 7=0000 ----->ADD. B (A 0)+, D 1 X=0 N=0 Z=1 V=0 C=0 Trace> PC=00040 E SR=2000 SS=00 A 00000 US=0000 A 0=00000417 A 1=0000 A 2=0000 A 3=0000 A 4=0000 A 5=0000 A 6=0000 A 7=00 A 00000 D 0=00000005 D 1=00000001 D 2=0000 D 3=0000 D 4=0000 D 5=0000 D 6=0000 D 7=0000 ----->SUBQ. B #$01, D 0 X=0 N=0 Z=0 V=0 C=0 Trace> PC=000410 SR=2000 SS=00 A 00000 US=0000 A 0=00000417 A 1=0000 A 2=0000 A 3=0000 A 4=0000 A 5=0000 A 6=0000 A 7=00 A 00000 D 0=00000004 D 1=00000001 D 2=0000 D 3=0000 D 4=0000 D 5=0000 D 6=0000 D 7=0000 ----->BNE. S $040 C X=0 N=0 Z=0 V=0 CPE/EE 421/521 Microcomputers This instruction adds the contents of the location pointed at by A 0 to D 1 Because the operand was (A 0)+, the contents of A 0 are incremented ADD. B (A 0)+, D 1 adds the source operand to D 1 58

Use of Address Register Indirect Addressing Trace> PC=00040 C SR=2000 SS=00 A 00000 US=0000 A 0=00000417 A 1=0000 A 2=0000 A 3=0000 A 4=0000 A 5=0000 A 6=0000 A 7=00 A 00000 D 0=00000004 D 1=00000001 D 2=0000 D 3=0000 D 4=0000 D 5=0000 D 6=0000 D 7=0000 ----->ADD. B (A 0)+, D 1 X=0 N=0 Z=0 V=0 C=0 Trace> PC=00040 E SR=2000 SS=00 A 00000 US=0000 A 0=00000418 A 1=0000 A 2=0000 A 3=0000 A 4=0000 A 5=0000 A 6=0000 A 7=00 A 00000 D 0=00000004 D 1=00000005 D 2=0000 D 3=0000 D 4=0000 D 5=0000 D 6=0000 D 7=0000 ----->SUBQ. B #$01, D 0 X=0 N=0 Z=0 V=0 C=0 On the next cycle the instruction ADD. B (A 0)+, D 1 uses A 0 as a source operand then increments the contents of A 0 Trace> PC=000410 SR=2000 SS=00 A 00000 US=0000 A 0=00000418 A 1=0000 A 2=0000 A 3=0000 A 4=0000 A 5=0000 A 6=0000 A 7=00 A 00000 D 0=00000003 D 1=00000005 D 2=0000 D 3=0000 D 4=0000 D 5=0000 D 6=0000 D 7=0000 ----->BNE. S $040 C X=0 N=0 Z=0 V=0 CPE/EE 421/521 Microcomputers 59

Problem Identify the source addressing mode used by each of the following instructions. ADD. B (A 5), (A 4) Address register indirect addressing. The address of the source operand is in A 5. MOVE. B #12, D 2 ADD. W TIME, D 4 MOVE. B D 6, D 4 MOVE. B (A 6)+, TEST Literal addressing. The source operand is the literal value 12. Memory direct addressing. The source operand is the contents of the memory location whose symbolic name is “TIME”. Data register direct. The source operand is the contents to D 6. Address register indirect with post-incrementing. The address of the source operand is in A 6. The contents of A 6 are incremented after the instruction. CPE/EE 421/521 Microcomputers 60

Problem If you were translating the following fragment of pseudocode into assembly language, what addressing modes are you most likely to use? SUM is a temporary variable. You can put it in a register and use register direct addressing J is a temporary variable that would normally be located in a register. SUM = 0 J is initialized to the literal value 5. FOR J = 5 TO 19 SUM = SUM + X(J)*Y(J) X(J) is an array element that would be accessed via address register indirect addressing. END FOR CPE/EE 421/521 Microcomputers 61

Other ARI Addressing Modes n Address Register Indirect with Predecrement Addressing MOVE. L –(A 0), D 3 (A 0 is first decremented by 4!) n n n Combination: MOVE. B (A 0)+, (A 1)+ MOVE. B –(A 1), (A 0)+ Register Indirect with Displacement Addressing d 16(Ai) RTL: ea=d 16+[Ai] Register Indirect with Index Addressing d 8(Ai, Xj. W) or d 8(Ai, Xj. L) RTL: ea=d 8+[Ai]+[Xj] CPE/EE 421/521 Microcomputers 62

Other ARI Addressing Modes n Program Counter Relative Addressing n Program Counter With Displacement d 16(PC) n Program Counter With Index d 16(PC) n RTL: ea=[PC]+d 16 RTL: ea=[PC]+[Xn]+d 16 PC can be used only for SOURCE OPERANDS MOVE. B … TABLE DC. B TABLE(PC), D 2 Value 1 Value 2 CPE/EE 421/521 Microcomputers 63

Summary Addressing Modes n n n Register direct addressing is used for variables that can be held in registers: ADD. B D 1, D 0 Literal (immediate) addressing is used for constants that do not change: ADD. B #24, D 0 Direct (absolute) addressing is used for variables that reside in memory: ADD. B 1000, D 0 Address Register Indirect: ADD. B (A 0), D 0 Autoincrement: ADD. B (A 0)+, D 0 CPE/EE 421/521 Microcomputers 64

Summary Addressing Modes n Address Register Indirect with Pre-decrement Addressing MOVE. L –(A 0), D 3 (A 0 is first decremented by 4!) n n n Combination: MOVE. B (A 0)+, (A 1)+ MOVE. B –(A 1), (A 0)+ Register Indirect with Displacement Addressing d 16(Ai) RTL: ea=d 16+[Ai] Register Indirect with Index Addressing d 8(Ai, Xj. W) or d 8(Ai, Xj. L) RTL: ea=d 8+[Ai]+[Xj] CPE/EE 421/521 Microcomputers 65

Summary Addressing Modes n Program Counter Relative Addressing n Program Counter With Displacement d 16(PC) n Program Counter With Index d 16(PC) n RTL: ea=[PC]+d 16 RTL: ea=[PC]+[Xn]+d 16 PC can be used only for SOURCE OPERANDS MOVE. B … TABLE DC. B TABLE(PC), D 2 Value 1 Value 2 CPE/EE 421/521 Microcomputers 66

Outline n n Programmer’s Model Assembly Language Directives Addressing Modes Instruction Set CPE/EE 421/521 Microcomputers 67

The 68000 Family Instruction Set n n Assumption: Students are familiar with the fundamentals of microprocessor architecture Groups of instructions: n n n Data movement Arithmetic operations Logical operations Shift operations Bit Manipulation Program Control Important NOTE: The contents of the CC byte of the SR are updated after the execution of an instruction. Refer to Table 2. 2 CPE/EE 421/521 Microcomputers 68

Data Movement Operations n n n n n Copy information from source to destination Comprises 70% of the average program MOVE/MOVEA MOVE to CCR MOVE <ea>, CCR – word instruction MOVE to/from SR MOVE <ea>, SR – in supervisor mode only; MOVE #$2700, SR – sets the 68 K in supervisor mode MOVE USP – to/from User Stack Pointer MOVE. L USP, A 3 - transfer the USP to A 3 MOVEQ – Move Quick(8 b #value to 32 b reg) MOVEM – to/from multiple registers (W/L) e. g. , MOVEM. L D 0 -D 5/A 0 -A 5, -(A 7) MOVEM. L (A 7)+, D 0 -D 5/A 0 -A 5 MOVEP – Move Peripheral CPE/EE 421/521 Microcomputers 69

Data Movement Operations, LEA n n Calculates an effective address and loads it into an address register – LEA <ea>, An Can be used only with 32 -bit operands Assembly language RTL LEA $0010 FFFF, A 5 [A 5] $0010 FFFF Load the address $0010 FFFF into register A 5. LEA $12(A 0, D 4. L), A 5 [A 5] $12 + [A 0] + [D 4] Load contents of A 0 plus contents of D 4 plus $12 into A 5. NOTE: If the instruction MOVEA. L $12(A 0, D 4), A 5 had been used, the contents of that address would have been deposited in A 5. n Why use it? FASTER! ADD. W $1 C(A 3, D 2), D 0 vs. LEA $1 C(A 3, D 2), A 5 ADD. W (A 5), D 0 CPE/EE 421/521 Microcomputers 70

Data Movement Operations, cont’d Moving data from a 32 -bit register to memory using the MOVEP instruction Bytes from the register are stored in every other memory byte CPE/EE 421/521 Microcomputers NOTE: The instruction takes 24 clock cycles to execute 71

An Example 68000 Registers D 0 01234567 D 4 33449127 A 0 00007020 A 4 00010020 Status register 2700 D 1 D 5 A 1 A 5 89 ABCDEF AAAA 00007000 00 FF 789 A D 2 D 6 A 2 A 6 0001002 D ABCD 0003 00007010 00010000 D 3 D 7 A 3 A 7 ABCD 7 FFF 5555 00007030 00010010 007021 007022 007023 007024 007025 007026 007027 007028 007029 00702 A 00702 B 00702 C 00702 D 00702 E 00702 F 007030 007031 007032 007033 007034 007035 007036 007037 007038 007039 00703 A 00703 B 00703 C 00703 D 00703 E 00703 F 5 A AD 99 92 79 33 97 14 79 E 7 00 0 A 88 18 82 79 23 17 46 9 E FC FF 77 60 21 42 55 EA 61 81 C 9 AA 010000 010001 010002 010003 010004 010005 010006 010007 010008 010009 01000 A 01000 B 01000 C 01000 D 01000 E 01000 F 010010 010011 010012 010013 010014 010015 010016 010017 010018 010019 01001 A 01001 B 01001 C 01001 D 01001 E 01001 F DD B 2 00 15 76 19 92 26 17 14 E 7 E 8 19 92 19 54 45 99 15 43 25 76 89 17 81 17 4 E 72 33 23 E 1 CD 010020 010021 010022 010023 010024 010025 010026 010027 010028 010029 01002 A 01002 B 01002 C 01002 D 01002 E 01002 F 010030 010031 010032 010033 010034 010035 010036 010037 010038 010039 01003 A 01003 B 01003 C 01003 D 01003 E 01003 F DC 25 15 17 29 39 49 2 D B 2 62 81 21 45 18 31 D 9 AA 77 78 AE EA 34 25 17 15 14 17 F 9 8 A 0 F F 2 E 5 Main memory 007000 007001 007002 007003 007004 007005 007006 007007 007008 007009 00700 A 00700 B 00700 C 00700 D 00700 E 00700 F 007010 007011 007012 007013 007014 007015 007016 007017 007018 007019 00701 A 00701 B 00701 C 00701 D 00701 E 00701 F AE F 2 32 77 89 90 1 A AE EE F 1 F 2 A 4 AE 88 AA E 4 7 E 8 D 9 C C 4 B 2 12 39 90 00 89 14 01 3 D 77 89 9 A CPE/EE 421/521 Microcomputers 72

An Example What is the effect of applying each of the following 68000 instructions assuming the initial condition shown before? Represent modified internal registers, memory locations and conditions. a) ORG $9000 LEA TABLE 1(PC), A 5 Assembly listing 1 00009000 ORG 2 00009000 4 BFA 0 FFE LEA $9000 TABLE 1(PC), A 5 EA = $00009000 + 2 + $0 FFE = $0000 A 000 A 5=$0000 A 000, CC: Not affected (NA) current PC value b) LEA 6(A 0, D 6. W), A 2 EA = 6 + $00007020 + $0003 = $00007029 offset A 2=$00007029 CC: NA A 0 D 6. W CPE/EE 421/521 Microcomputers 73

Data Movement Operations, cont’d n PEA: Push Effective Address n n n EXG (EXG Xi, Xj) n n Calculates an effective address and pushes it onto the stack pointed at by A 7 – PEA <ea> Can be used only with 32 -bit operands Exchanges the entire 32 -bit contents of two registers SWAP (SWAP Di) n Exchanges the upper- and lower-order words of a DATA register CPE/EE 421/521 Microcomputers 74

Integer Arithmetic Operations n n n n Float-point operations not directly supported Except for division, multiplication, and if destination is Ai, all act on 8 -, 16 -, and 32 -bit values ADD/ADDA (no mem-to-mem additions, if destination is Ai, use ADDA) ADDQ (adds a small 3 -bit literal quickly) ADDI (adds a literal value to the destination) ADDX (adds also the contents of X bit to the sum) used for multi-precision addition CLR (clear specified data register or memory location) equivalent to MOVE #0, <ea> for address registers use SUB. L An, An CPE/EE 421/521 Microcomputers 75

Integer Arithmetic Operations, cont’d n DIVU/DIVS – unsigned/2’s-complement numbers n n n MULU/MULS – unsigned/2’s-complement numbers n n n DIVU <ea>, Dn or DIVS <ea>, Dn 32 -bit longword in Dn is divided by the 16 -bit word at <ea> 16 -bit quotient is deposited in the lower-order word of Dn The remainder is stored in the upper-order word of Dn Low-order 16 -bit word in Dn is multiplied by the 16 -bit word at <ea> 32 -bit product is deposited in Dn SUB, SUBA, SUBQ, SUBI, SUBX NEG – forms the 2’s complement of an operand NEG <ea> NEGX – Negate with Extend, used for multi-prec. arith. EXT – Sign Extend EXT. W Dn copies bit 7 to bits 8 -15 EXT. L Dn copies bit 15 to bits 16 -31 CPE/EE 421/521 Microcomputers 76

BCD Arithmetic Operations n Only 3 instructions support BCD n n ABCD Di, Dj or ABCD –(Ai), -(Aj) Add BCD with extend – adds two packed BCD digits together with X bit from the CCR SBCD – similar [destination]-[source]-[X] NBCD <ea> subtracts the specified operand from zero together with X bit and forms the 10’s complement of the operand if X =0, or 9’s complement if X =1 Involve X because they are intended to be used in operations on a string of BCD digits CPE/EE 421/521 Microcomputers 77

Logical Operations n n n Standard AND, OR, EOR, and NOT Immediate operand versions: ANDI, ORI, EORI AND a bit with 0 – mask OR a bit with 1 – set EOR a bit with 1 – toggle Logical operations affect the CCR in the same way as MOVE instructions CPE/EE 421/521 Microcomputers 78

Shift Operations n Logical Shift n n LSL – Logical Shift Left LSR – Logical Shift Right CPE/EE 421/521 Microcomputers 79

Shift Operations, cont’d n Arithmetic Shift n n ASL – Arithmetic Shift Left ASR – Arithmetic Shift Right CPE/EE 421/521 Microcomputers 80

Shift Operations, cont’d n Rotate n n ROL – Rotate Left ROR – Rotate Right CPE/EE 421/521 Microcomputers 81

Shift Operations, cont’d n Rotate Through Extend n n ROXL – Rotate Left Through Extend ROXR – Rotate Right Through Extend CPE/EE 421/521 Microcomputers 82

Effect of the Shift Instructions ASL Initial Value 11101011 01111110 After First Shift 11010110 11111100 CCR XNZVC 11001 01010 After Second Shift 10101100 11111000 CCR XNZVC 11001 11011 ASR 11101011 01111110101 00111111 11001 00000 11111010 00011111 11001 10001 LSL 11101011 01111110 11010110 111111001 01000 10101100 11111000 11001 LSR 11101011 01111110 01110101 00111111 10001 00000 00111010 00011111 10001 ROL 11101011 01111110 11010111 11111100 ? 1001 ? 1000 101011111001 ? 1001 ROR 11101011 01111110101 00111111 ? 1001 ? 0000 11111010 10011111 ? 1001 CPE/EE 421/521 Microcomputers 83

Forms of Shift Operations n Mode 1 ASL Dx, Dy n Shift Dy by Dx bits Mode 2 ASL #<data>, Dy n Shift Dy by #data bits Mode 3 ASL <ea> Shift the contents at the effective address by one place All three modes apply to all eight shift instructions CPE/EE 421/521 Microcomputers 84

Bit Manipulation Operations n Act on a single bit of an operand: 1. 2. 1. 2. 3. 4. 5. 6. The complement of the selected bit is moved to the Z bit (Z set if specified bit is zero) The bit is either unchanged, set, cleared, or toggled NVCX bits are not affected May be applied to a bit within byte or longword BTST – Bit Test only BSET – Bit Test and Set (specified bit set) BCLR – Bit Test and Clear (specified bit cleared) CPE/EE 421/521 Microcomputers 85 BCHG – Bit Test and Change (specified bit

Bit Manipulation Operations, cont’d n All 4 have the same assembly language forms: BTST Dn, <ea> or BTST #<data>, <ea> Location of the bit to be tested Effective address of the operand CPE/EE 421/521 Microcomputers 86

Program Control Operations n n Examine bits in CCR and chose between two courses of action CCR bits are either: n n n Updated after certain instruction have been executed, or Explicitly updated (bit test, compare, or test instructions) Compare instructions: CMP, CMPA, CMPI, CMPM n n Subtract the contents of one register (or mem. location) from another register (or mem. location) Update NZVC bits of the CCR X bit of the CCR is unaffected The result of subtraction is ignored CPE/EE 421/521 Microcomputers 87

Program Control Operations, cont’d n n n CMP: CMP <ea 1>, <ea 2> [<ea 2>]-[<ea 1>] CMPI: CMP #<data>, <ea> comparison with a literal CMPA: CMP <ea>, An used for addresses, operates only on word and longword operands CMPM: CMP (Ai)+, (Aj)+ compares memory with memory, one of few that works only with operands located in memory TST: TST <ea> zero is subtracted from specified operand; N and Z are set accordingly, V and C are cleared, X is unchanged Except CMPA, all CPE/EE take 421/521 byte, Microcomputers word, or longword operands 88

Program Control Operations, cont’d n Branch Instructions n n n Branch Conditionally Branch Unconditionally Test Condition, Decrement, and Branch BRANCH CONDITIONALLY Bcc <label> n n n cc stands for one of 14 logical conditions (Table 2. 4) Automatically calculated displacement can be d 8 or d 16 Displacement is 2’s complement signed number 8 -bit displacement can be forced by adding. S extension ZNCV bits are used to decide CPE/EE 421/521 Microcomputers 89

Program Control Operations, cont’d n n BRANCH UNCONDITIONALLY BRA <label> or JMP (An) JMP d 16(An) JMP d 8(An, Xi) JMP Absolute_address JMP d 16(PC) JMP d 8(PC, Xi) TEST CONDITION, DECREMENT, and BRANCH DBcc Dn, <label> (16 bit displacement only) One of 14 values from Table 2. 4, plus T, plus F If test is TRUE, branch is NOT taken ! If cc is NOT TRUE, Dn is decremented by 1; If Dn is now equal to – 1 next instruction is executed if not, branch to <label is taken> CPE/EE 421/521 Microcomputers 90

Stack Pointer First-in-last-out n SP points to the element at the top of the stack n Up to eight stacks simultaneously n A 7 used for subroutines n A 7 automatically adjusted by 2 or 4 for L or W ops. n Push/pull implementation: MOVE. W Dn, -(A 7) <-PUSH MOVE. W (A 7)+, Dn <-PULL n SSP/USP n CPE/EE 421/521 Microcomputers Figure 2. 18 91

Subroutines n BRANCH TO SUBROUTINE BSR <label> n = [A 7] - 4 M([A 7])] [PC] + d 8 RETURN FROM SUBROUTINE RTS = [PC] [M([A 7])] [A 7] + 4 CPE/EE 421/521 Microcomputers 92

Subroutines, cont’d n BRANCH TO SUBROUTINE 000 FFA 41 F 900004000 LEA TABLE, A 0 001000 61000206 Next. Chr BSR Get. Char 001004 10 C 0 MOVE. B D 0, (A 0) 001006 0 C 00000 D CMP. B #$0 D, D 0 00100 A 66 F 4 BNE Next. Chr 001102 61000104 BSR Get. Chr 001106 0 C 000051 CMP. B #’Q’, D 0 00110 A 67000 EF 4 BEQ QUIT 001208 1239000080000 Get. Chr MOVE. B ACIAC, D 0 BSR d 8=? (or d 16, to specify d 8 use BSR. S) d 8 = $00001208 – ($00001000 + 2) = $00000206 current PC value CPE/EE 421/521 Microcomputers 93

Nested Subroutines CPE/EE 421/521 Microcomputers 94

Nested Subroutines, cont’d CPE/EE 421/521 Microcomputers 95

Nested Subroutines, cont’d n Returning directly to a higher-level subroutine Sub 2 Exit n . . BEQ. . RTS LEA RTS Exit 4(A 7), A 7 RTR (Return and restore condition codes) n Save the condition code register on the stack: MOVE CCR, -(A 7) n Use RTR instead of RTS CPE/EE 421/521 Microcomputers 96

Miscellaneous Instructions n Scc: Set byte conditionally Scc <ea> (cc same as in DBcc) If the condition is TRUE, all the bits of the byte specified by <ea> are SET, if the condition is FALSE, bits are CLEARED n n NOP: No Operation RTS: Return from Subroutine STOP: STOP #n Stop and load n into Status Register; n is 16 -bit number; Privileged instruction CHK, RESET, RTE, TAS, TRAPV - later CPE/EE 421/521 Microcomputers 97

Example: Linked List n Adding an element to the end of a linked list n n LEA * LOOP EXIT HEAD points to the first element, NEW contains the address of the new item to be inserted Longwords HEAD, A 0 TST. L (A 0) BEQ EXIT MOVEA. L (A 0), A 0 BRA LOOP LEA NEW, A 1 MOVE. L A 1, (A 0) CLR. L (A 1) A 0 initially points to the start of the linked list IF the address field = 0 THEN exit ELSE read the address of the next element Continue Pick up address of new element Add new entry to end of list Insert the new terminator CPE/EE 421/521 Microcomputers 98

Example: Linked List, cont’d n Initial linked list: LEA * LOOP EXIT HEAD, A 0 TST. L (A 0) BEQ EXIT MOVEA. L (A 0), A 0 BRA LOOP LEA NEW, A 1 MOVE. L A 1, (A 0) CLR. L (A 1) A 0 initially points to the start of the linked list IF the address field = 0 THEN exit ELSE read the address of the next element Continue Pick up address of new element Add new entry to end of list Insert the new terminator CPE/EE 421/521 Microcomputers 99

Example: Linked List , cont’d n Linked list after inserting an element at the end: LEA * LOOP EXIT HEAD, A 0 TST. L (A 0) BEQ EXIT MOVEA. L (A 0), A 0 BRA LOOP LEA NEW, A 1 MOVE. L A 1, (A 0) CLR. L (A 1) A 0 initially points to the start of the linked list IF the address field = 0 THEN exit ELSE read the address of the next element Continue Pick up address of new element Add new entry to end of list Insert the new terminator CPE/EE 421/521 Microcomputers 100

Example: Linked List , Memory Map CPE/EE 421/521 Microcomputers 101