CPE 631 Multiprocessors and ThreadLevel Parallelism Electrical and

CPE 631: Multiprocessors and Thread-Level Parallelism Electrical and Computer Engineering University of Alabama in Huntsville Aleksandar Milenkovic, milenka@ece. uah. edu http: //www. ece. uah. edu/~milenka UAH-CPE 631

Growth in processor performance From Hennessy and Patterson, Computer Architecture: A Quantitative Approach, 4 th edition, October, 2006 AM La. CASA • VAX : 25%/year 1978 to 1986 • RISC + x 86: 52%/year 1986 to 2002 • RISC + x 86: 20%/year 2002 to present 2

Déjà vu all over again? n “… today’s processors … are nearing an impasse as technologies approach the speed of light. . ” n n “We are dedicating all of our future product development to multicore designs. … This is a sea change in computing” n AM La. CASA David Mitchell, The Transputer: The Time Is Now (1989) Transputer had bad timing (Uniprocessor performance ) Procrastination rewarded: 2 X seq. perf. / 1. 5 years Paul Otellini, President, Intel (2005) All microprocessor companies switch to MP (2 X CPUs / 2 yrs) Procrastination penalized: 2 X sequential perf. / 5 yrs Manufacturer/Year AMD/’ 05 Intel/’ 06 IBM/’ 04 Sun/’ 05 Processors/chip 2 2 2 8 Threads/Processor 1 2 2 4 Threads/chip 2 4 4 32 3

Other Factors Favoring Multiprocessing n n A growing interest in servers (and their performance) A growth in data intensive applications n n n AM La. CASA n data bases, file servers, game servers, . . . An insight that we do not care that much about further improving desktop performance (except for graphics) An improved understanding in how to effectively use multiprocessors in server environments (a lot of thread-level parallelism) The advantages of leveraging a design investment by replication rather than unique design 4

Parallel Computers n Definition: “A parallel computer is a collection of processing elements that cooperate and communicate to solve large problems fast. ” Almasi and Gottlieb, Highly Parallel Computing , 1989 n Questions about parallel computers: n n n AM La. CASA n n How large a collection? How powerful are processing elements? How do they cooperate and communicate? How are data transmitted? What type of interconnection? What are HW and SW primitives for programmer? Does it translate into performance? 5

Flynn’s Taxonomy M. J. Flynn, "Very High-Speed Computers", Proc. of the IEEE, V 54, 1900 -1909, Dec. 1966. Flynn classified by data and control streams in 1966 Single Instruction Single Data (SISD) (Uniprocessor) Multiple Instruction Single Data (MISD) (? ? ) AM La. CASA Single Instruction Multiple Data SIMD (single PC: Vector, CM -2) Multiple Instruction Multiple Data MIMD (Clusters, SMP servers) 6

Flynn’s Tahonomy (cont’d) n SISD (Single Instruction Single Data) n n MISD (Multiple Instruction Single Data) n n La. CASA same instruction is executed by multiple processors using different data Adv. : simple programming model, low overhead, flexibility, all custom integrated circuits Examples: Illiac-IV, CM-2 MIMD (Multiple Instruction Multiple Data) n AM multiple processors on a single data stream; SIMD (Single Instruction Multiple Data) n n uniprocessors n n n each processor fetches its own instructions and operates on its own data Examples: Sun Enterprise 5000, Cray T 3 D, SGI Origin Adv. : flexible, use off-the-shelf micros MIMD current winner (< 128 processor MIMD machines) 7

MIMD: An Architecture of Choice for General-purpose Multiprocessors n Why is it the choice for general-purpose multiprocessors n Flexible n n n Cost-effective: use off-the-shelf processors Major MIMD Styles n AM La. CASA Can function as single-user machines focusing on highperformance for one application, Multiprogrammed machine running many tasks simultaneously, or Some combination of these two n Centralized shared memory ("Uniform Memory Access" time or "Shared Memory Processor") Decentralized memory (memory module with CPU) 8

2 Classes of Multiprocessors (wrt. memory) n n AM La. CASA Centralized Memory Multiprocessor n < few dozen processor chips (and < 100 cores) in 2006 n Small enough to share single, centralized memory Physically Distributed-Memory multiprocess n Larger number chips and cores than 1. n BW demands Memory distributed among processors 9

Centralized vs. Distributed Memory Scale P 0 P 1 C C M Pn. . . C IO Centralized Memory M P 0 P 1 Pn C C C IO M IO . . . M IO Interconnection Network Distributed Memory AM La. CASA 10

Centralized Memory Multiprocessor n n AM La. CASA Also called symmetric multiprocessors (SMPs) because single main memory has a symmetric relationship to all processors Large caches single memory can satisfy memory demands of small number of processors Can scale to a few dozen processors by using a switch and by using many memory banks Although scaling beyond that is technically conceivable, it becomes less attractive as the number of processors sharing centralized memory increases 11

Distributed Memory Multiprocessor n Pro: Cost-effective way to scale memory bandwidth n n n AM La. CASA n If most accesses are to local memory Pro: Reduces latency of local memory accesses Con: Communicating data between processors more complex Con: Must change software to take advantage of increased memory BW 12

2 Models for Communication and Memory Architecture n n Communication occurs by explicitly passing messages among the processors: message-passing multiprocessors Communication occurs through a shared address space (via loads and stores); shared memory multiprocessors either n n n UMA (Uniform Memory Access time) for shared address, centralized memory MP NUMA (Non Uniform Memory Access time multiprocessor) for shared address, distributed memory MP In past, confusion whether “sharing” means sharing physical memory (Symmetric MP) or sharing address space AM La. CASA 13

Challenges of Parallel Processing n n First challenge is % of program inherently sequential Suppose 80 X speedup from 100 processors. What fraction of original program can be sequential? n n 10% 5% 1% <1% AM La. CASA 14

Challenges of Parallel Processing n n n Second challenge is long latency to remote memory Suppose 32 CPU MP, 2 GHz, 200 ns remote memory, all local accesses hit memory hierarchy and base CPI is 0. 5. (Remote access = 200/0. 5 = 400 clock cycles. ) What is performance impact if 0. 2% instructions involve remote access? n n AM La. CASA n 1. 5 X 2. 0 X 2. 5 X 16

Challenges of Parallel Processing n n n Application parallelism primarily via new algorithms that have better parallel performance Long remote latency impact both by architect and by the programmer For example, reduce frequency of remote accesses either by n n AM n La. CASA Caching shared data (HW) Restructuring the data layout to make more accesses local (SW) Today’s lecture on HW to help latency via caches 18

Symmetric Shared-Memory Architectures n n From multiple boards on a shared bus to multiple processors inside a single chip Caches both n n n AM La. CASA Private data are used by a single processor Shared data are used by multiple processors Caching shared data reduces latency to shared data, memory bandwidth for shared data, and interconnect bandwidth cache coherence problem 19

Example Cache Coherence Problem P 2 P 1 u=? $ P 3 3 u=? 4 $ 5 $ u : 5 u = 7 u : 5 I/O devices 1 u : 5 2 Memory n AM La. CASA n Processors see different values for u after event 3 With write back caches, value written back to memory depends on happenstance of which cache flushes or writes back value when n n Processes accessing main memory may see very stale value Unacceptable for programming, and its frequent! 20

Example P 1 P 2 /*Assume initial value of A and flag is 0*/ A = 1; while (flag == 0); /*spin idly*/ flag = 1; n n Intuition not guaranteed by coherence expect memory to respect order between accesses to different locations issued by a given process n AM La. CASA n print A; to preserve orders among accesses to same location by different processes Coherence is not enough! n P 1 Pn pertains only to single location Conceptual Picture Mem 21

Intuitive Memory Model P L 1 100: 67 L 2 100: 35 Memory Disk n 1. 2. AM La. CASA n n Reading an address should return the last value written to that address n Easy in uniprocessors, except for I/O 100: 34 Too vague and simplistic; 2 issues Coherence defines values returned by a read Consistency determines when a written value will be returned by a read Coherence defines behavior to same location, Consistency defines behavior to other locations 22

Defining Coherent Memory System n n n AM La. CASA Preserve Program Order: A read by processor P to location X that follows a write by P to X, with no writes of X by another processor occurring between the write and the read by P, always returns the value written by P Coherent view of memory: Read by a processor to location X that follows a write by another processor to X returns the written value if the read and write are sufficiently separated in time and no other writes to X occur between the two accesses Write serialization: 2 writes to same location by any 2 processors are seen in the same order by all processors n If not, a processor could keep value 1 since saw as last write n For example, if the values 1 and then 2 are written to a location, processors can never read the value of the location as 2 and then later read it as 1 23

Write Consistency n n AM n La. CASA For now assume A write does not complete (and allow the next write to occur) until all processors have seen the effect of that write The processor does not change the order of any write with respect to any other memory access if a processor writes location A followed by location B, any processor that sees the new value of B must also see the new value of A These restrictions allow the processor to reorder reads, but forces the processor to finish writes in program order 24

Basic Schemes for Enforcing Coherence n Program on multiple processors will normally have copies of the same data in several caches n n Rather than trying to avoid sharing in SW, SMPs use a HW protocol to maintain coherent caches n n AM La. CASA Migration and Replication key to performance of shared data Migration - data can be moved to a local cache and used there in a transparent fashion n n Unlike I/O, where its rare Reduces both latency to access shared data that is allocated remotely and bandwidth demand on the shared memory Replication – for shared data being simultaneously read, since caches make a copy of data in local cache n Reduces both latency of access and contention for read shared data 25

2 Classes of Cache Coherence Protocols n n Directory based — Sharing status of a block of physical memory is kept in just one location, the directory Snooping — Every cache with a copy of data also has a copy of sharing status of block, but no centralized state is kept n n AM La. CASA All caches are accessible via some broadcast medium (a bus or switch) All cache controllers monitor or snoop on the medium to determine whether or not they have a copy of a block that is requested on a bus or switch access 26

Snoopy Cache-Coherence Protocols State Address Data n Cache Controller “snoops” all transactions on the shared medium (bus or switch) n n relevant transaction if for a block it contains take action to ensure coherence n AM La. CASA n n invalidate, update, or supply value depends on state of the block and the protocol Either get exclusive access before write via write invalidate or update all copies on write 27

Example: Write-through Invalidate P 2 P 1 u=? $ P 3 3 u=? 4 $ 5 $ u : 5 u = 7 u : 5 I/O devices 1 u : 5 2 u=7 Memory n AM La. CASA n Must invalidate before step 3 Write update uses more broadcast medium BW all recent MPUs use write invalidate 28

Architectural Building Blocks n Cache block state transition diagram n FSM specifying how disposition of block changes n n Broadcast Medium Transactions (e. g. , bus) n n n La. CASA n Fundamental system design abstraction Logically single set of wires connect several devices Protocol: arbitration, command/addr, data Every device observes every transaction Broadcast medium enforces serialization of read or write accesses Write serialization n AM invalid, dirty 1 st processor to get medium invalidates others copies Implies cannot complete write until it obtains bus All coherence schemes require serializing accesses to same cache block Also need to find up-to-date copy of cache block 29

Locate up-to-date copy of data n Write-through: get up-to-date copy from memory n n Write-back harder n n La. CASA n Most recent copy can be in a cache Can use same snooping mechanism n AM Write through simpler if enough memory BW Snoop every address placed on the bus If a processor has dirty copy of requested cache block, it provides it in response to a read request and aborts the memory access Complexity from retrieving cache block from a processor cache, which can take longer than retrieving it from memory Write-back needs lower memory bandwidth Support larger numbers of faster processors Most multiprocessors use write-back 30

Cache Resources for WB Snooping n n Normal cache tags can be used for snooping Valid bit per block makes invalidation easy Read misses easy since rely on snooping Writes Need to know if know whether any other copies of the block are cached n AM La. CASA n No other copies No need to place write on bus for WB Other copies Need to place invalidate on bus 31

Cache Resources for WB Snooping n To track whether a cache block is shared, add extra state bit associated with each cache block, like valid bit and dirty bit n n AM La. CASA n n Write to Shared block Need to place invalidate on bus and mark cache block as private (if an option) No further invalidations will be sent for that block This processor called owner of cache block Owner then changes state from shared to unshared (or exclusive) 32

Cache behavior in response to bus n Every bus transaction must check the cache-address tags n n A way to reduce interference is to duplicate tags n n could potentially interfere with processor cache accesses One set for caches access, one set for bus accesses Another way to reduce interference is to use L 2 tags n n n Since L 2 less heavily used than L 1 Every entry in L 1 cache must be present in the L 2 cache, called the inclusion property If Snoop gets a hit in L 2 cache, then it must arbitrate for the L 1 cache to update the state and possibly retrieve the data, which usually requires a stall of the processor AM La. CASA 33

Example Protocol n n Snooping coherence protocol is usually implemented by incorporating a finite-state controller in each node Logically, think of a separate controller associated with each cache block n n AM La. CASA That is, snooping operations or cache requests for different blocks can proceed independently In implementations, a single controller allows multiple operations to distinct blocks to proceed in interleaved fashion n that is, one operation may be initiated before another is completed, even through only one cache access or one bus access is allowed at time 34

Write-through Invalidate Protocol n 2 states per block in each cache n n n AM La. CASA as in uniprocessor state of a block is a p-vector of states Hardware state bits associated with blocks that are in the cache other blocks can be seen as being in invalid (not-present) state in that cache Writes invalidate all other cache copies n can have multiple simultaneous readers of block, but write invalidates them Pr. Rd/ -Pr. Wr / Bus. Wr Pr. Rd: Processor Read Pr. Wr: Processor Write Bus. Rd: Bus Read Bus. Wr: Bus Write V Bus. Wr / - Pr. Rd / Bus. Rd I Pr. Wr / Bus. Wr State Tag Data Pn P 1 $ Bus Mem $ I/O devices 35

Is 2 -state Protocol Coherent? n n Processor only observes state of memory system by issuing memory operations Assume bus transactions and memory operations are atomic and a one-level cache n n all phases of one bus transaction complete before next one starts processor waits for memory operation to complete before issuing next with one-level cache, assume invalidations applied during bus transaction All writes go to bus + atomicity Writes serialized by order in which they appear on bus (bus order) => invalidations applied to caches in bus order n n How to insert reads in this order? n n AM La. CASA n Important since processors see writes through reads, so determines whether write serialization is satisfied But read hits may happen independently and do not appear on bus or enter directly in bus order Let’s understand other ordering issues 36

Ordering n n AM La. CASA Writes establish a partial order Doesn’t constrain ordering of reads, though shared-medium (bus) will order read misses too n any order among reads between writes is fine, as long as in program order 37

Example Write Back Snoopy Protocol n n n AM La. CASA n n Invalidation protocol, write-back cache n Snoops every address on bus n If it has a dirty copy of requested block, provides that block in response to the read request and aborts the memory access Each memory block is in one state: n Clean in all caches and up-to-date in memory (Shared) n OR Dirty in exactly one cache (Exclusive) n OR Not in any caches Each cache block is in one state (track these): n Shared: block can be read n OR Exclusive: cache has only copy, its writeable, and dirty n OR Invalid: block contains no data (in uniprocessor cache too) Read misses: cause all caches to snoop bus Writes to clean blocks are treated as misses 38

Write-Back State Machine - CPU Read hit n n State machine for CPU requests Invalid for each cache block Non-resident blocks invalid CPU Write CPU Read Place read miss on bus Shared (read/only) Place Write Miss on bus Cache Block State AM La. CASA CPU read hit CPU write hit CPU Write Place Write Miss on Bus Exclusive (read/write) CPU Write Miss (? ) Write back cache block Place write miss on bus 39

Write-Back State Machine- Bus request n State machine for bus requests for each cache block Invalid Write miss for this block Write Back Block; (abort memory access) AM La. CASA Exclusive (read/write) Write miss for this block Shared (read/only) Read miss for this block Write Back Block; (abort memory access) 40

Block-replacement n State machine for CPU requests for each cache block Invalid CPU Read hit CPU Read Place read miss on bus Shared (read/only) CPU Write Place Write Miss on bus Cache Block State AM La. CASA CPU read hit CPU write hit CPU read miss CPU Read miss Write back block, Place read miss on bus CPU Write Place Write Miss on Bus Exclusive (read/write) CPU Write Miss Write back cache block Place write miss on bus 41

Write-back State Machine-III n Write miss State machine for this block for CPU requests CPU Read Invalid for each Place read miss cache block and on bus CPU Write for bus requests Place Write for each Miss on bus cache block Write miss CPU read miss for this block Write Back Block; (abort memory access) Cache Block State AM La. CASA CPU Read hit CPU read hit CPU write hit Shared (read/only) CPU Read miss Place read miss on bus Write back block, Place read miss CPU Write on bus Place Write Miss on Bus Exclusive (read/write) Read miss for this block Write Back Block; (abort memory access) CPU Write Miss Write back cache block Place write miss on bus 42

Example Processor 1 Processor 2 Assumes initial cache state is invalid and A 1 and A 2 map to same cache block, but A 1 != A 2 AM La. CASA Bus CPU Read hit Remote Write Shared Invalid Remote Write Back Read miss on bus Write miss on bus Remote Read Write Back Memory CPU Read Miss CPU Write Place Write Miss on Bus Exclusive CPU read hit CPU write hit CPU Write Miss Write Back 43

Example: Step 1 Assumes initial cache state is invalid and A 1 and A 2 map to same cache block, but A 1 != A 2. Active arrow = AM La. CASA CPU Read hit Remote Write Shared Invalid Remote Write Back Read miss on bus Write miss on bus Remote Read Write Back CPU Read Miss CPU Write Place Write Miss on Bus Exclusive CPU read hit CPU write hit CPU Write Miss Write Back 44

Example: Step 2 Assumes initial cache state is invalid and A 1 and A 2 map to same cache block, but A 1 != A 2 AM La. CASA CPU Read hit Remote Write Shared Invalid Remote Write Back Read miss on bus Write miss on bus Remote Read Write Back CPU Read Miss CPU Write Place Write Miss on Bus Exclusive CPU read hit CPU write hit CPU Write Miss Write Back 45

Example: Step 3 A 1 Assumes initial cache state is invalid and A 1 and A 2 map to same cache block, but A 1 != A 2. AM La. CASA CPU Read hit Remote Write Shared Invalid Remote Write Back Read miss on bus Write miss on bus Remote Read Write Back CPU Read Miss CPU Write Place Write Miss on Bus Exclusive CPU read hit CPU write hit CPU Write Miss Write Back 46

Example: Step 4 A 1 A 1 Assumes initial cache state is invalid and A 1 and A 2 map to same cache block, but A 1 != A 2 AM La. CASA CPU Read hit Remote Write Shared Invalid Remote Write Back Read miss on bus Write miss on bus Remote Read Write Back CPU Read Miss CPU Write Place Write Miss on Bus Exclusive CPU read hit CPU write hit CPU Write Miss Write Back 47

Example: Step 5 A 1 A 1 A 1 Assumes initial cache state is invalid and A 1 and A 2 map to same cache block, but A 1 != A 2 Shared Invalid Remote Write Back AM La. CASA CPU Read hit Remote Write Read miss on bus Write miss on bus Remote Read Write Back CPU Read Miss CPU Write Place Write Miss on Bus Exclusive CPU read hit CPU write hit CPU Write Miss Write Back 48

Implementation Complications n Write Races: n Cannot update cache until bus is obtained n n Two step process: n n n AM La. CASA Arbitrate for bus Place miss on bus and complete operation If miss occurs to block while waiting for bus, handle miss (invalidate may be needed) and then restart Split transaction bus: n n n Otherwise, another processor may get bus first, and then write the same cache block! Bus transaction is not atomic: can have multiple outstanding transactions for a block Multiple misses can interleave, allowing two caches to grab block in the Exclusive state Must track and prevent multiple misses for one block Must support interventions and invalidations 49

Implementing Snooping Caches n n n Multiple processors must be on bus, access to both addresses and data Add a few new commands to perform coherency, in addition to read and write Processors continuously snoop on address bus n n Since every bus transaction checks cache tags, could interfere with CPU just to check: n AM La. CASA If address matches tag, either invalidate or update n solution 1: duplicate set of tags for L 1 caches just to allow checks in parallel with CPU solution 2: L 2 cache already duplicate, provided L 2 obeys inclusion with L 1 cache n block size, associativity of L 2 affects L 1 50

Implementing Snooping Caches n n Bus serializes writes, getting bus ensures no one else can perform memory operation On a miss in a write back cache, may have the desired copy and its dirty, so must reply Add extra state bit to cache to determine shared or not Add 4 th state (MESI) AM La. CASA 51

MESI: CPU Requests CPU Read hit CPU Read Bus. Rd / No. Sh Invalid CPU Write /Bus. Rd. Ex CPU Read miss Bus. Rd / No. Sh Exclusive CPU read miss Bus. WB, Bus. Rd / No. Sh CPU write hit /CPU read miss Bus. WB, Bus. Rd / Sh CPU read hit CPU write hit AM La. CASA Modified (read/write) CPU read miss Bus. WB, Bus. Rd / Sh CPU Write Miss Bus. Rd. Ex CPU Write Hit Bus. Inv Shared CPU Read hit 52

MESI: Bus Requests Invalid Bus. Rd. Ex Exclusive Bus. Rd / => Sh Bus. Rd. Ex / =>Bus. WB AM La. CASA Modified (read/write) Bus. Rd / =>Bus. WB Shared 53

Limitations in Symmetric Shared-Memory Multiprocessors and Snooping Protocols n n Single memory accommodate all CPUs Multiple memory banks Bus-based multiprocessor, bus must support both coherence traffic & normal memory traffic Multiple buses or interconnection networks (cross bar or small point-to-point) Opteron n n AM La. CASA n Memory connected directly to each dual-core chip Point-to-point connections for up to 4 chips Remote memory and local memory latency are similar, allowing OS Opteron as UMA computer 54

Performance of Symmetric Shared. Memory Multiprocessors n n n Cache performance is combination of Uniprocessor cache miss traffic Traffic caused by communication n n Results in invalidations and subsequent cache misses 4 th C: coherence miss n Joins Compulsory, Capacity, Conflict AM La. CASA 55

Coherency Misses n True sharing misses arise from the communication of data through the cache coherence mechanism n n False sharing misses when a block is invalidated because some word in the block, other than the one being read, is written into n n AM La. CASA Invalidates due to 1 st write to shared block Reads by another CPU of modified block in different cache Miss would still occur if block size were 1 word Invalidation does not cause a new value to be communicated, but only causes an extra cache miss Block is shared, but no word in block is actually shared miss would not occur if block size were 1 word 56

Example: True v. False Sharing v. Hit? • Assume x 1 and x 2 in same cache block. P 1 and P 2 both read x 1 and x 2 before. Time P 1 1 Write x 1 2 3 Write x 1 AM La. CASA False miss; x 1 irrelevant to P 2 Write x 2 Read x 2 True, False, Hit? Why? True miss; invalidate x 1 in P 2 Read x 2 4 5 P 2 False miss; x 1 irrelevant to P 2 True miss; invalidate x 2 in P 1 57

• True sharing and false sharing unchanged going from 1 MB to 8 MB (L 3 cache) • Uniprocessor cache misses improve with cache size increase (Instruction, Capacity/Conflict, Compulsory) (Memory) Cycles per Instruction MP Performance 4 Processor Commercial Workload: OLTP, Decision Support (Database), Search Engine AM La. CASA 58

MP Performance 2 MB Cache Commercial Workload: OLTP, Decision Support (Database), Search Engine (Memory) Cycles per Instruction • True sharing, false sharing increase going from 1 to 8 CPUs AM La. CASA 59

Conclusions n n n AM La. CASA n “End” of uniprocessors speedup => Multiprocessors Parallelism challenges: % parallalizable, long latency to remote memory Centralized vs. distributed memory n Small MP vs. lower latency, larger BW for Larger MP Message Passing vs. Shared Address n Uniform access time vs. Non-uniform access time Snooping cache over shared medium for smaller MP by invalidating other cached copies on write Sharing cached data Coherence (values returned by a read), Consistency (when a written value will be returned by a read) Shared medium serializes writes Write consistency 60

Distributed Memory Machines n Nodes include processor(s), some memory, typically some IO, and interface to an interconnection network M P 0 P 1 Pn C C C IO M IO . . . M C - Cache M - Memory IO - Input/Output IO Interconnection Network AM La. CASA Pro: Cost effective approach to scale memory bandwidth Pro: Reduce latency for accesses to local memory Con: Communication complexity 61

Directory Protocol n Similar to Snoopy Protocol: Three states n n n In addition to cache state, must track which processors have data when in the shared state (usually bit vector, 1 if processor has copy) Keep it simple(r): n AM La. CASA Shared: ≥ 1 processors have data, memory up-to-date Uncached (no processor has it; not valid in any cache) Exclusive: 1 processor (owner) has data; memory out-of-date n n Writes to non-exclusive data => write miss Processor blocks until access completes Assume messages received and acted upon in order sent 62

Directory Protocol n No bus and don’t want to broadcast: n n n Terms: typically 3 processors involved n n n AM La. CASA n interconnect no longer single arbitration point all messages have explicit responses Local node where a request originates Home node where the memory location of an address resides Remote node has a copy of a cache block, whether exclusive or shared Example messages on next slide: P = processor number, A = address 63

Directory Protocol Messages Message type Source Destination Msg Content Read miss Local cache Home directory P, A Processor P reads data at address A; make P a read sharer and arrange to send data back Write miss Local cache Home directory P, A Processor P writes data at address A; make P the exclusive owner and arrange to send data back Invalidate Home directory Remote caches A Invalidate a shared copy at address A. Fetch Home directory Remote cache A Fetch the block at address A and send it to its home directory Fetch/Invalidate Home directory Remote cache A Fetch the block at address A and send it to its home directory; invalidate the block in the cache AM Data value reply Home directory La. CASA Local cache Data Return a data value from the home memory (read miss response) Data write-back Remote cache Home directory A, Data Write-back a data value for address A (invalidate response) 64

State Transition Diagram for an Individual Cache Block in a Directory Based System n n n AM La. CASA States identical to snoopy case; transactions very similar Transitions caused by read misses, write misses, invalidates, data fetch requests Generates read miss & write miss msg to home directory Write misses that were broadcast on the bus for snooping => explicit invalidate & data fetch requests Note: on a write, a cache block is bigger, so need to read the full cache block 65

CPU -Cache State Machine n n Invalidate State machine for CPU requests for each memory block Invalid state if in memory Invalid Fetch/Invalidate send Data Write Back message to home directory AM La. CASA Shared (read/only) CPU Read Send Read Miss message CPU read miss: Send Read Miss CPU Write: Send Write Miss message msg to h. d. Exclusive (read/writ) CPU read hit CPU write hit CPU Read hit to home directory Fetch: send Data Write Back message to home directory CPU read miss: send Data Write Back message and read miss to home directory CPU write miss: send Data Write Back message and Write Miss to home directory 66

State Transition Diagram for the Directory n n Same states & structure as the transition diagram for an individual cache 2 actions: update of directory state & send msgs to statisfy requests Tracks all copies of memory block. Also indicates an action that updates the sharing set, Sharers, as well as sending a message. AM La. CASA 67

Directory State Machine n n State machine for Directory requests for each memory block Uncached state if in memory Uncached Data Write Back: Sharers = {} (Write back block) Write Miss: Sharers = {P}; AM send Fetch/Invalidate; send Data Value Reply msg to remote cache La. CASA Read miss: Sharers = {P} send Data Value Reply Write Miss: Sharers = {P}; send Data Value Reply msg Exclusive (read/writ) Read miss: Sharers += {P}; send Data Value Reply Shared (read only) Write Miss: send Invalidate to Sharers; then Sharers = {P}; send Data Value Reply msg Read miss: Sharers += {P}; send Fetch; send Data Value Reply msg to remote cache (Write back block) 68

Example Directory Protocol n Message sent to directory causes two actions: n n n Block is in Uncached state: the copy in memory is the current value; only possible requests for that block are: n n n Read miss: requesting processor sent data from memory &requestor made only sharing node; state of block made Shared. Write miss: requesting processor is sent the value & becomes the Sharing node. The block is made Exclusive to indicate that the only valid copy is cached. Sharers indicates the identity of the owner. Block is Shared => the memory value is up-to-date: n AM La. CASA Update the directory More messages to satisfy request n Read miss: requesting processor is sent back the data from memory & requesting processor is added to the sharing set. Write miss: requesting processor is sent the value. All processors in the set Sharers are sent invalidate messages, & Sharers is set to identity of requesting processor. The state of the block is made Exclusive. 69

Example Directory Protocol n Block is Exclusive: current value of the block is held in the cache of the processor identified by the set Sharers (the owner) => three possible directory requests: n n AM La. CASA n Read miss: owner processor sent data fetch message, causing state of block in owner’s cache to transition to Shared and causes owner to send data to directory, where it is written to memory & sent back to requesting processor. Identity of requesting processor is added to set Sharers, which still contains the identity of the processor that was the owner (since it still has a readable copy). State is shared. Data write-back: owner processor is replacing the block and hence must write it back, making memory copy up-to-date (the home directory essentially becomes the owner), the block is now Uncached, and the Sharer set is empty. Write miss: block has a new owner. A message is sent to old owner causing the cache to send the value of the block to the directory from which it is sent to the requesting processor, which becomes the new owner. Sharers is set to identity of new owner, and state of block is made Exclusive. 70

Example Processor 1 Processor 2 Interconnect Directory Memory P 2: Write 20 to A 1 AM La. CASA A 1 and A 2 map to the same cache block 71

Example Processor 1 Processor 2 Interconnect Directory Memory P 2: Write 20 to A 1 AM La. CASA A 1 and A 2 map to the same cache block 72

Example Processor 1 Processor 2 Interconnect Directory Memory P 2: Write 20 to A 1 AM La. CASA A 1 and A 2 map to the same cache block 73

Example Processor 1 Processor 2 Interconnect Directory Memory A 1 P 2: Write 20 to A 1 Write Back AM La. CASA A 1 and A 2 map to the same cache block 74

Example Processor 1 Processor 2 Interconnect Directory Memory A 1 P 2: Write 20 to A 1 AM La. CASA A 1 and A 2 map to the same cache block 75

Example Processor 1 Processor 2 Interconnect Directory Memory A 1 P 2: Write 20 to A 1 AM La. CASA A 1 and A 2 map to the same cache block 76

Implementing a Directory n n We assume operations atomic, but they are not; reality is much harder; must avoid deadlock when run out of buffers in network (see Appendix I) – The devil is in the details Optimizations: n AM La. CASA read miss or write miss in Exclusive: send data directly to requestor from owner vs. 1 st to memory and then from memory to requestor 77

Parallel Program: An Example /* * Title: Matrix multiplication kernel * Author: Aleksandar Milenkovic, milenkovic@computer. org * Date: November, 1997 * *------------------------------* Command Line Options * -p. P: P = number of processors; must be a power of 2. * -n. N: N = number of columns (even integers). * -h : Print out command line options. *------------------------------* */ void main(int argc, char*argv[]) { /* Define shared matrix */ ma = (double **) G_MALLOC(N*sizeof(double *)); mb = (double **) G_MALLOC(N*sizeof(double *)); AM La. CASA for(i=0; i<N; i++) { ma[i] = (double *) G_MALLOC(N*sizeof(double)); mb[i] = (double *) G_MALLOC(N*sizeof(double)); }; /* Initialize the Index */ Index = 0; /* Initialize the barriers and the lock */ LOCKINIT(index. Lock) BARINIT(bar_fin) /* read/initialize data */. . . /* do matrix multiplication in parallel a=a*b */ /* Create the slave processes. */ for (i = 0; i < num. Procs-1; i++) CREATE(Slave. Start) /* Make the master do slave work so we don't waste a processor */ Slave. Start(); . . . } 78

Parallel Program: An Example /*====== Slave. Start ========*/ /* This is the routine that each processor will be executing in parallel */ void Slave. Start() { int my. Index, i, j, k, begin, end; double tmp; /* the main body of a thread */ for(i=begin; i<end; i++) { for(j=0; j<N; j++) { tmp=0. 0; for(k=0; k<N; k++) { tmp = tmp + ma[i][k]*mb[k][j]; } ma[i][j] = tmp; } LOCK(index. Lock); /* enter the critical section */ my. Index = Index; /* read your ID */ ++Index; /* increment it, so the next will operate on ID+1 */ UNLOCK(index. Lock); /* leave the critical section */ AM La. CASA /* Initialize begin and end */ begin = (N/num. Procs)*my. Index; end = (N/num. Procs)*(my. Index+1); } BARRIER(bar_fin, num. Procs); } 79

Synchronization n n Why Synchronize? Need to know when it is safe for different processes to use shared data Issues for Synchronization: n n n AM La. CASA Uninterruptable instruction to fetch and update memory (atomic operation); User level synchronization operation using this primitive; For large scale MPs, synchronization can be a bottleneck; techniques to reduce contention and latency of synchronization 80

Uninterruptable Instruction to Fetch and Update Memory n Atomic exchange: interchange a value in a register for a value in memory n n n AM La. CASA n 0 => synchronization variable is free 1 => synchronization variable is locked and unavailable Set register to 1 & swap New value in register determines success in getting lock 0 if you succeeded in setting the lock (you were first) 1 if other processor had already claimed access Key is that exchange operation is indivisible Test-and-set: tests a value and sets it if the value passes the test Fetch-and-increment: it returns the value of a memory location and atomically increments it n 0 => synchronization variable is free 81

User Level Synchronization— Operation Using this Primitive n n Spin locks: processor continuously tries to acquire, spinning around a loop trying to get the lock li R 2, #1 lockit: exch R 2, 0(R 1) ; atomic exchange bnez R 2, lockit ; already locked? What about MP with cache coherency? n n AM La. CASA Want to spin on cache copy to avoid full memory latency Likely to get cache hits for such variables Problem: exchange includes a write, which invalidates all other copies; this generates considerable bus traffic Solution: start by simply repeatedly reading the variable; when it changes, then try exchange (“test and test&set”): try: li R 2, #1 lockit: lw R 3, 0(R 1) ; load var bnez R 3, lockit ; not free=>spin exch R 2, 0(R 1) ; atomic exchange bnez R 2, try ; already locked? 82

Lock&Unlock: Test&Set /* Test&Set */ ======= loadi R 2, #1 lockit: exch R 2, location /* atomic operation*/ bnez R 2, lockit /* test*/ unlock: 0) */ store location, #0 /* free the lock (write AM La. CASA 83

Lock&Unlock: Test and Test&Set /* Test and Test&Set */ ============ lockit: load R 2, location /* read lock varijable */ bnz R 2, lockit /* check value */ loadi R 2, #1 exch R 2, location /* atomic operation */ bnz reg, lockit /* if lock is not acquired, repeat */ AM La. CASA unlock: 0) */ store location, #0 /* free the lock (write 84

Lock&Unlock: Test and Test&Set /* Load-linked and Store-Conditional */ ==================== lockit: ll R 2, location /* load-linked read */ bnz R 2, lockit /* if busy, try again */ load R 2, #1 sc location, R 2 /* conditional store */ beqz R 2, lockit /* if sc unsuccessful, try again */ AM La. CASA unlock: store location, #0 /* store 0 */ 85

Uninterruptable Instruction to Fetch and Update Memory n n Hard to have read & write in 1 instruction: use 2 instead Load linked (or load locked) + store conditional n n AM La. CASA Load linked returns the initial value Store conditional returns 1 if it succeeds (no other store to same memory location since preceeding load) and 0 otherwise Example doing atomic swap with LL & SC: try: mov R 3, R 4 ; mov exchange value ll R 2, 0(R 1) ; load linked sc R 3, 0(R 1) ; store conditional (returns 1, if Ok) beqz R 3, try ; branch store fails (R 3 = 0) mov R 4, R 2 ; put load value in R 4 Example doing fetch & increment with LL & SC: try: ll R 2, 0(R 1) ; load linked addi R 2, #1 ; increment (OK if reg–reg) sc R 2, 0(R 1) ; store conditional beqz R 2, try ; branch store fails (R 2 = 0) 86

Barrier Implementation struct Barrier. Struct { LOCKDEC(counterlock); LOCKDEC(sleeplock); int sleepers; }; . . . #define BARDEC(B) struct Barrier. Struct B; #define BARINIT(B) sys_barrier_init(&B); #define BARRIER(B, N) sys_barrier(&B, N); AM La. CASA 87

Barrier Implementation (cont’d) void sys_barrier(struct Barrier. Struct *B, int N) { LOCK(B->counterlock) (B->sleepers)++; if (B->sleepers < N ) { UNLOCK(B->counterlock) LOCK(B->sleeplock) B->sleepers--; if(B->sleepers > 0) UNLOCK(B->sleeplock) else UNLOCK(B->counterlock) } else { B->sleepers--; if(B->sleepers > 0) UNLOCK(B->sleeplock) else UNLOCK(B->counterlock) } AM La. CASA } 88

Another MP Issue: Memory Consistency Models n n What is consistency? When must a processor see the new value? e. g. , seems that P 1: A = 0; P 2: B = 0; . . A = 1; B = 1; L 1: if (B == 0). . . L 2: if (A == 0). . . Impossible for both if statements L 1 & L 2 to be true? n n n AM La. CASA What if write invalidate is delayed & processor continues? Memory consistency models: what are the rules for such cases? Sequential consistency: result of any execution is the same as if the accesses of each processor were kept in order and the accesses among different processors were interleaved => assignments before ifs above n SC: delay all memory accesses until all invalidates done 89

Memory Consistency Model n n n AM La. CASA n Schemes faster execution to sequential consistency Not really an issue for most programs; they are synchronized n A program is synchronized if all access to shared data are ordered by synchronization operations write (x). . . release (s) {unlock}. . . acquire (s) {lock}. . . read(x) Only those programs willing to be nondeterministic are not synchronized: “data race”: outcome f(proc. speed) Several Relaxed Models for Memory Consistency since most programs are synchronized; characterized by their attitude towards: RAR, WAR, RAW, WAW to different addresses 90