CPE 323 Introduction to Embedded Computer Systems The
CPE 323 Introduction to Embedded Computer Systems: The MSP 430 System Architecture Instructor: Dr Aleksandar Milenkovic Lecture Notes CPE 323
Outline n n n MSP 430: System Architecture System Resets, Interrupts, and Operating Modes Basic Clock Module Watchdog Timer CPE 323 2
MSP 430: System Resets, Interrupts, and Operating Modes CPE 323
Resets n n Reset – a sequence of operations that put device into a well-defined state (from which the user’s program may start) Performed when n Power is first applied and Device detects serious fault in hardware or software from which the user’s program cannot be expected to recover MSP 430 supports two types of reset (HW and SW controlled) n n Power-on Reset (POR) Power-up Clear (PUC) CPE 323 4
Power-on Reset (POR) n n Generated by the following severe conditions related to hardware Device is powered-up. POR us raised if the supply voltage drops to so low a value that the device may not work correctly. Include brownout detector. A low external signal on the #RST/NMI pin (if the pin is configured for the reset function rather than the nonmaskable interrupt). Active by default Some MSP 430 s have a more comprehensive supply voltage supervisor (SVS). It sets the SVSFG flag if the voltage falls below the programmed level and can optionally reset the device CPE 323 5
Power-Up Clear (PUC) n n n It always follows the POR. It is generated when software appears to be out of control Watchdog time overflows in watchdog mode Write into the watchdog control register (WDTCTL) with incorrect password in the upper byte. Can be triggered even if the WDT is disabled or operates in the interval mode n n Write an incorrect password into the flash memory controller registers (FCTLn) n n Correct password is 0 x 5 A available as symbol WDTPW Protects the stored program from a runaway software In newer devices, a PUC is triggered when we try to fetch an instruction from the range of addresses reserved for peripheral I/O or for unimplemented memory CPE 323 6
System Reset n Power-on Reset (POR) n n n Powering up the device A low signal on the RST/NMI pin when configured in the reset mode An SVS low condition when PORON=1. n Power-up Clear n n CPE 323 A POR signal Watchdog timer expiration when in watchdog mode only Watchdog timer security key violation A Flash memory security key violation 7
Power-On Reset (POR) CPE 323 8
Brownout Reset CPE 323 9
Conditions after Reset n n Initial conditions for all registers and peripherals after POR and PUC are specified in the family’s user guides; some common effects #RST/NMI pin is configured for reset Most I/O pins are configured as digital inputs For registers see the manual. Notation is as follows n n n rw-0: means that a bit can be read and written and is initialized to 0 after a PUC rw-(0): means that a bit can be read and written and is initialized to 0 after a POR and retains its value after a PUC Status register is cleared (R 2=0): active mode WDT starts in watchdog mode PC is loaded with the reset vector which is @0 x. FFFE CPE 323 10
Reset related flags n n How to identify a source of the reset when debugging IFG – Interrupt Flag Register (IFG 1, IFG 2) n n n WDTIFG: shows that the WDT timed out or its security key is violated OFIFG: indicates an oscillator fault (causes a nonmaskable interrupt, not reset) RSTIFG: indicates a reset caused by a signal on the #RST/NMI pin PORIFG: is set on power-on reset NMIIFG: flags a non-maskable interrupt caused by a signal on #RST/NMI These bits are not cleared by a PUC, so they can be tested to identify the source of the PUC CPE 323 11
Software configuration n n n Your SW must configure the MSP 430 Initialize the SP, typically to the top of RAM Configure the watchdog to the requirements of the application Setup the clock (clocks) Configure all ports (unused pins should never be left as floating inputs). Configure peripheral modules to the requirements of the application (e. g. Timer. A, ADC 12, . . . ) Finally enable interrupts if needed Note: Additionally, the watchdog timer, oscillator fault, and flash memory flags can be evaluated to determine the source of the reset CPE 323 12
Interrupts n 3 types n n System reset (Non)-maskable NMI Maskable Interrupt priorities are fixed and defined by the arrangement of modules CPE 323 13
(Non)-Maskable Interrupts (NMI) n Sources n n An edge on the RST/NMI pin when configured in NMI mode An oscillator fault occurs An access violation to the flash memory Are not masked by GIE (General Interrupt Enable), but are enabled by individual interrupt enable bits (NMIIE, OFIE, ACCVIE) CPE 323 14
NMI Interrupt Handler CPE 323 15
Maskable Interrupts n n n Caused by peripherals with interrupt capability Each can be disabled individually by an interrupt enable bit All can be disabled by GIE bit in the status register CPE 323 16
Interrupt acceptance n n n n 1) Any currently executing instruction is completed. 2) The PC, which points to the next instruction, is pushed onto the stack. 3) The SR is pushed onto the stack. 4) The interrupt with the highest priority is selected if multiple interrupts occurred during the last instruction and are pending for service. 5) The interrupt request flag resets automatically on single-source flags. Multiple source flags remain set for servicing by software. 6) The SR is cleared with the exception of SCG 0, which is left unchanged. This terminates any low-power mode. Because the GIE bit is cleared, further interrupts are disabled. 7) The content of the interrupt vector is loaded into the PC: the program continues with the interrupt service routine at that address. Takes 6 cc to execute CPE 323 17
Return from Interrupt n RETI - Return from Interrupt Service Routine n n n 1) The SR with all previous settings pops from the stack. All previous settings of GIE, CPUOFF, etc. are now in effect, regardless of the settings used during the interrupt service routine. 2) The PC pops from the stack and begins execution at the point where it was interrupted. Takes 5 cc to execute CPE 323 18
Interrupt Vectors CPE 323 19
Interrupt Service Routines n Interrupt Service Routine declaration // Func. declaration Interrupt[int_vector] void my. ISR (Void); Interrupt[int_vector] void my. ISR (Void) { // ISR code } q EXAMPLE Interrupt[TIMERA 0_VECTOR] void my. ISR (Void); Interrupt[TIMERA 0_VECTOR] void my. ISR (Void) { // ISR code } CPE 323 20
Interrupt Vectors /****************************** * Interrupt Vectors (offset from 0 x. FFE 0) ******************************/ #define #define #define #define PORT 2_VECTOR UART 1 TX_VECTOR UART 1 RX_VECTOR PORT 1_VECTOR TIMERA 0_VECTOR ADC_VECTOR UART 0 TX_VECTOR UART 0 RX_VECTOR WDT_VECTOR COMPARATORA_VECTOR TIMERB 1_VECTOR TIMERB 0_VECTOR NMI_VECTOR RESET_VECTOR 1 * 2 2 * 2 3 * 2 4 * 2 5 * 2 6 * 2 7 * 2 8 * 2 9 * 2 10 * 2 11 * 2 12 * 2 13 * 2 14 * 2 15 * 2 /* /* /* /* 0 x. FFE 2 0 x. FFE 4 0 x. FFE 6 0 x. FFE 8 0 x. FFEA 0 x. FFEC 0 x. FFEE 0 x. FFF 0 0 x. FFF 2 0 x. FFF 4 0 x. FFF 6 0 x. FFF 8 0 x. FFFA 0 x. FFFC 0 x. FFFE CPE 323 Port 2 */ UART 1 Transmit */ UART 1 Receive */ Port 1 */ Timer A CC 1 -2, TA */ Timer A CC 0 */ ADC */ UART 0 Transmit */ UART 0 Receive */ Watchdog Timer */ Comparator A */ Timer B 1 -7 */ Timer B 0 */ Non-maskable */ Reset [Highest Pr. ] */ 21
Operating Modes (to be discussed later) CPE 323 22
MSP 430: Clock System CPE 323
Clock System: An Introduction n Clock – square wave whose edges trigger hardware Traditional clocks: a crystal with frequency of a few MHz is connected to two C pins; internally the clock may be divided by 2 or 4. Typical application cycle in embedded systems n n C stays in a low-power mode until An event wakes up C to handle it Often need multiple clocks (fast for CPU, slow for peripherals) Power consumption: P ~ CV 2 f CPE 323 24
Clock System: An Introduction n Crystal clocks n n Accurate (the frequency is typically within 11 part in 100, 000), stable (do not change with time or temperature) High-frequency (a few MHz) or low-frequency (32, 768 Hz) for a real-time clock Expensive, delicate, draw a relatively large current, require additional components (capacitors), take long time to start up and stabilize Resistor and capacitor (RC) clocks n n n Cheap, quick to start Poor accuracy and stability Can be external or integrated into a chip CPE 323 25
MS 430 Clock System n n n Flexible to address conflicting demands for highperformance, low-power, and a precise frequency 3 internal clocks from 4 possible sources: MCLK, SMCLK, ACLK Master clock, MCLK: used by the CPU and a few peripherals (e. g. , ADC 12, DMA, . . . ) Subsystem master clock, SMCLK: distributed to peripherals Auxiliary clock, ACLK: distributed to peripherals Typical configuration: MCLK and SMCLK are in the megahertz range, ACLK is 32 KHz CPE 323 26
Clock System: MSP 430 n Digitally controlled Oscillator, DCO: available in all devices; highlycontrollable oscillator n n Low- or high-frequency crystal oscillator, LFXT 1 n n Generated on-chip RC-type frequency controlled by SW + HW LF: 32768 Hz XT: 450 k. Hz. . 8 MHz High-frequency crystal oscillator, XT 2 Internal very low-power, lowfrequency oscillator, VLO: available in more recent MSP 430 F 2 xx devices; provides an alternative to LFXT 1 when accuracy is not needed CPE 323 27
Basic Clock System: MSP 430 x 1 xx n n DCOCLK Generated on-chip with 6 s start-up 32 KHz Watch Crystal - or - High Speed Crystal / Resonator to 8 MHz n n n (our system is 4 MHz/8 MHz high Speed Crystal) Flexible clock distribution tree for CPU and peripherals Programmable open-loop DCO Clock with internal and external current source LFXT 1 oscillator 32 k. Hz XIN LFXT 1 CLK 8 MHz XOUT ACLK Auxiliary Clock to peripherals LFXT 2 CLK Clock Distribution 100 k. Hz - 5 MHZ Rosc Digital Controlled Oscillator DCOCLK DCO CPE 323 MCLK Main System Clock to CPU SMCLK Sub-System Clock to peripherals 28
Basic Clock System – Block Diagram DIVA 2 LFXTCLK Osc. Off /1, /2, /4, /8 XTS ACLKGEN ACLK Auxiliary Clock SELM DIVM CPUOff High frequency 2 XT oscillator, XTS=1 Vcc 2 DCO MOD 3 0 P 2. 5 /Rosc 0, 1 Low power Vcc LF oscillator, XTS=0 Rsel SCG 0 1 DCOR DCGenerator DCGEN 2 3 5 /1, /2, /4, /8, off MCLKGEN Main System Clock SELS DIVS SCG 1 DCOCLK 2 Digital Controlled Oscillator DCO 0 Modulator MOD 1 + DCOMOD /1, /2, /4, /8, off SMCLKGEN SMCLK Sub-System Clock The DCO-Generator is connected to pin P 2. 5/Rosc if DCOR control bit is set. The port pin P 2. 5/Rosc is selected if DCOR control bit is reset (initial state). CPE 323 29
Basic clock block diagram (MSP 430 x 13 x/14 x/15 x/16 x) CPE 323 30
Basic operation n n After POC (Power Up Clear) MCLK and SMCLK are sourced by DCOCLK (approx. 800 KHz) and ACLK is sourced by LFXT 1 in LF mode Status register control bits SCG 0, SCG 1, OSCOFF, and CPUOFF configure the MSP 430 operating modes and enable or disable portions of the basic clock module n n n SCG 1 - when set, turns off the SMCLK SCG 0 - when set, turns off the DCO dc generator (if DCOCLK is not used for MCLK or SMCLK) OSCOFF - when set, turns off the LFXT 1 crystal oscillator (if LFXT 1 CLK is not use for MCLK or SMCLK) CPUOFF - when set, turns off the CPU DCOCTL, BCSCTL 1, and BCSCTL 2 registers configure the basic clock module The basic clock can be configured or reconfigured by software at any time during program execution CPE 323 31
Basic Clock Module - Control Registers The Basic Clock Module is configured using control registers DCOCTL, BCSCTL 1, and BCSCTL 2, and four bits from the CPU status register: SCG 1, SCG 0, Osc. Off, and CPUOFF. User software can modify these control registers from their default condition at any time. The Basic Clock Module control registers are located in the byte-wide peripheral map and should be accessed with byte (. B) instructions. Register State DCO control register Basic clock system control 1 Basic clock system control 2 Short Form Register Type Address DCOCTL Read/write 056 h 060 h BCSCTL 1 Read/write 057 h 084 h BCSCTL 2 Read/write 058 h reset CPE 323 Initial State 32
Basic Clock Module - Control Registers n n n BCSCTL 2 Direct SW Control DCOCLK can be Set - Stabilized Stable DCOCLK over Temp/Vcc. 058 h SELM. 1 SELM. 0 DIVM. 1 DIVM. 0 SELS rw-0 BCSCTL 1 DCOCTL 057 h 056 h XT 2 Off XTS DIVA. 1 DIVA. 0 XT 5 V rw-(1) rw-(0) rw-0 Rsel. 2 Rsel. 1 Rsel. 0 rw-1 rw-0 Selection of DCO nominal frequency rw-0 DIVS. 1 DIVS. 0 DCOR rw-0 DCO. 2 DCO. 1 DCO. 0 MOD. 4 MOD. 3 MOD. 2 MOD. 1 MOD. 0 rw-1 rw-0 Which of eight discrete DCO frequencies is selected rw-0 Define how often frequency f. DCO+1 within the period of 32 DCOCLK cycles is used. Remaining clock cycles (32 -MOD) the frequency f. DCO is mixed RSEL. x Select DCO nominal frequency DCO. x and MOD. x set exact DCOCLK … select other clock tree options CPE 323 33
DCOCTL n Digitally-Controlled Oscillator (DCO) Clock-Frequency Control DCOCTL is loaded with a value of 060 h with a valid PUC condition. 7 0 DCOCTL DCO. 2 DCO. 1 DCO. 0 MOD. 4 MOD. 3 MOD. 2 MOD. 1 MOD. 0 056 H 0 1 1 0 0 0 MOD. 0. . MOD. 4: The MOD constant defines how often the discrete frequency f. DCO+1 is used within a period of 32 DCOCLK cycles. During the remaining clock cycles (32–MOD) the discrete frequency f DCO is used. When the DCO constant is set to seven, no modulation is possible since the highest feasible frequency has then been selected. DCO. 0. . DCO. 2: The DCO constant defines which one of the eight discrete frequencies is selected. The frequency is defined by the current injected into the dc generator. CPE 323 34
BCSCTL 1 n Oscillator and Clock Control Register BCSCTL 1 is affected by a valid PUC or POR condition. 7 0 BCSCTL 1 XT 2 Off XTS DIVA. 1 DIVA. 0 XT 5 V Rsel. 2 Rsel. 1 Rsel. 0 057 h 1 0 0 Bit 0 to Bit 2: The internal resistor is selected in eight different steps. Rsel. 0 to Rsel. 2 The value of the resistor defines the nominal frequency. The lowest nominal frequency is selected by setting Rsel=0. Bit 3, XT 5 V: XT 5 V should always be reset. Bit 4 to Bit 5: The selected source for ACLK is divided by: DIVA = 0: 1 DIVA = 1: 2 DIVA = 2: 4 DIVA = 3: 8 CPE 323 35
BCSCTL 1 Bit 6, XTS: The LFXT 1 oscillator operates with a low-frequency or with a highfrequency crystal: XTS = 0: The low-frequency oscillator is selected. XTS = 1: The high-frequency oscillator is selected. The oscillator selection must meet the external crystal’s operating condition. Bit 7, XT 2 Off: The XT 2 oscillator is switched on or off: XT 2 Off = 0: the oscillator is on XT 2 Off = 1: the oscillator is off if it is not used for MCLK or SMCLK. CPE 323 36
BCSCTL 2 is affected by a valid PUC or POR condition. 7 0 BCSCTL 2 SELM. 1 SELM. 0 DIVM. 1 DIVM. 0 SELS DIVS. 1 DIVS. 0 DCOR 058 h Bit 0, DCOR: The DCOR bit selects the resistor for injecting current into the dc generator. Based on this current, the oscillator operates if activated. DCOR = 0: Internal resistor on, the oscillator can operate. The fail-safe mode is on. DCOR = 1: Internal resistor off, the current must be injected externally if the DCO output drives any clock using the DCOCLK. Bit 1, Bit 2: The selected source for SMCLK is divided by: DIVS. 1. . DIVS. 0 DIVS = 0: 1 DIVS = 1: 2 DIVS = 2: 4 DIVS = 3: 8 CPE 323 37
BCSCTL 2 Bit 3, SELS: Selects the source for generating SMCLK: SELS = 0: Use the DCOCLK SELS = 1: Use the XT 2 CLK signal (in three-oscillator systems) or LFXT 1 CLK signal (in two-oscillator systems) Bit 4, Bit 5: The selected source for MCLK is divided by DIVM. 0. . DIVM. 1 DIVM = 0: 1 DIVM = 1: 2 DIVM = 2: 4 DIVM = 3: 8 Bit 6, Bit 7: Selects the source for generating MCLK: SELM. 0. . SELM. 1 SELM = 0: Use the DCOCLK SELM = 1: Use the DCOCLK SELM = 2: Use the XT 2 CLK (x 13 x and x 14 x devices) or Use the LFXT 1 CLK (x 11 x(1) devices) SELM = 3: Use the LFXT 1 CLK CPE 323 38
Range (RSELx) and Steps (DCOx) CPE 323 39
F 149 default DCO clock setting CPE 323 slas 272 c/page 46 40
External Resistor n n The DCO temperature coefficient can be reduced by using an external resistor ROSC to source the current for the DC generator. ROSC also allows the DCO to operate at higher frequencies. n n Internal resistor nominal value is approximately 200 k. Ohm => DCO to operate up to 5 MHz. External ROSC of approximately 100 k. Ohm => the DCO can operate up to approximately 10 MHz. CPE 323 41
Basic Clock Systems-DCO TAPS Ø DCOCLK frequency control v nominal - injected current into DC generator 1) internal resistors Rsel 2, Rsel 1 and Rsel 0 2) an external resistor at Rosc (P 2. 5/11 x) v Control bits DCO 0 to DCO 2 set f. DCO tap v Modulation bits MOD 0 to MOD 4 allow mixing of f. DCO and f. DCO+1 for precise frequency generation Example Selected: f 3: f 4: MOD=19 Frequency Cycle time 1000 k. Hz 1000 nsec 943 k. Hz 1042 k. Hz 1060 nsec 960 nsec DCOCLK f nominal+1 Selected f nominal-1 DCOCLK DCO +1 +0 Modulation Period f 0 f 1 f 2 f 3 f 4 f 5 To produce an intermediate effective frequency between f. DCO and f. DCO+1 Cycle_time = ((32 -MOD)*t. DCO+MOD*t. DCO+1)/32 = 1000. 625 ns, selected frequency 1 MHz. CPE 323 f 6 f 7 f. DCO 42
Software FLL Ø Basic Clock DCO is an open loop - close with SW+HW v A reference frequency e. g. ACLK or 50/60 Hz can be used to measure DCOCLK’s v Initialization or Periodic software set and stabilizes DCOCLK over reference clock v DCOCLK is programmable 100 k. Hz - 5 Mhz and stable over voltage and temperature reference clock e. g. ACLK or 50/60 Hz SW+HW Controls the DCOCLK Vcc Rsel SCG 0 MOD DCO 3 0 P 2. 5 /Rosc 1 DCOR DCGenerator 5 Digital Controlled Oscillator DCOCLK + Modulator MOD DCGEN DCOMOD CPE 323 43
Software FLL Implementation Ø Example: Set DCOCLK= 1228800, ACLK= 32768 v ACLK/4 captured on CCI 2 B, DCOCLK is clock source for Timer_A v Comparator 2 HW captures SMCLK (1228800 Hz) in one ACLK/4 (8192 Hz) period v Target Delta = 1228800/8192= 150 CCI 2 BInt … cmp jlo Dec. DCO dec reti Inc. DCO inc reti #150, Delta Inc. DCO &DCOCTL ; ; &DCOCTL ; Increase DCOCLK Delta Compute Delta= 1228800/8192 JMP to Inc. DCO Decrease DCOCLK Target 1228800 Hz DCOCLK source for timer 15 0 CCI 2 B 1 2 3 Stable reference ACLK/4, 8192 Hz source CPE 323 Capture Mode 0 Capture/Compare Register CCR 2 Capture 15 0 Comparator 2 44
Fail Safe Operation n Basic module incorporates an oscillator-fault detection fail-safe feature. The oscillator fault detector is an analog circuit that monitors the LFXT 1 CLK (in HF mode) and the XT 2 CLK. An oscillator fault is detected when either clock signal is not present for approximately 50 us. n n When an oscillator fault is detected, and when MCLK is sourced from either LFXT 1 in HF mode or XT 2, MCLK is automatically switched to the DCO for its clock source. When OFIFG is set and OFIE is set, an NMI interrupt is requested. The NMI interrupt service routine can test the OFIFG flag to determine if an oscillator fault occurred. The OFIFG flag must be cleared by software. CPE 323 45
Synchronization of clock signals n When switching MCLK and SMCLK from one clock source to another => avoid race conditions n n n The current clock cycle continues until the next rising edge The clock remains high until the next rising edge of the new clock The new clock source is selected and continues with a full high period CPE 323 46
Basic Clock Module - Examples Ø How to select the Crystal Clock BCSCTL 1 |= XTS; BCSCTL 1 |= DIVA 0; BCSCTL 1 |= DIVA 1; do { IFG 1 &= ~OFIFG; for (i = 0 x. FF; i > 0; i--); } while ((IFG 1 & OFIFG)); // clock is stable BCSCTL 2 |= SELM_3; // ACLK = LFXT 1 = HF XTAL // ACLK = XT 1 / 8 // Clear OSCFault flag from SW // Time for flag to set by HW // OSCFault flag still set? // MCLK = LFXT 1 (safe) CPE 323 47
Basic Clock Systems-Examples Ø Adjusting the Basic Clock The control registers of the Basic Clock are under full software control. If clock requirements other than those of the default from PUC are necessary, the Basic Clock can be configured or reconfigured by software at any time during program execution. q ACLKGEN from LFXT 1 crystal, resonator, or external-clock source and divided by 1, 2, 4, or 8. If no LFXTCLK clock signal is needed in the application, the Osc. Off bit should be set in the status register. q SCLKGEN from LFXTCLK, DCOCLK, or XT 2 CLK (x 13 x and x 14 x only) and divided by 1, 2, 4, or 8. The SCG 1 bit in the status register enables or disables SMCLK. q MCLKGEN from LFXTCLK, DCOCLK, or XT 2 CLK (x 13 x and x 14 x only) and divided by 1, 2, 4, or 8. When set, the CPUOff bit in the status register enables or disables MCLK. q DCOCLK frequency is adjusted using the RSEL, DCO, and MOD bits. The DCOCLK clock source is stopped when not used, and the dc generator can be disabled by the SCG 0 bit in the status register (when set). q The XT 2 oscillator sources XT 2 CLK (x 13 x and x 14 x only) by clearing the XT 2 Off bit. CPE 323 48
FLL+ Clock Module (MSP 430 x 4 xx) n FLL+ clock module: frequency-locked loop clock module n n n Low system cost Ultra-low power consumption Can operate with no external components Supports one or two external crystals or resonators (LFXT 1 and XT 2) Internal digitally-controlled oscillator with stabilization to a multiple of the LFXT 1 watch crystal frequency Full software control over 4 output clocks: ACLK, ACLK/n, MCLK, and SMCLK CPE 323 49
MSP 430 x 43 x, MSP 430 x 44 x and MSP 430 x 461 x Frequency-Locked Loop CPE 323 50
FLL+ Clock Module n LFXT 1 CLK: Low-frequency/high-frequency oscillator that can be used n n n either with low-frequency 32768 -Hz watch crystals, or standard crystals or resonators in the 450 -k. Hz to 8 -MHz range. XT 2 CLK: Optional high-frequency oscillator that can be used with standard crystals, resonators, or external clock sources in the 450 -k. Hz to 8 -MHz range. In MSP 430 F 47 x devices the upper limit is 16 MHz. DCOCLK: Internal digitally controlled oscillator (DCO) with RC-type characteristics, stabilized by the FLL. Four clock signals are available from the FLL+ module: n n ACLK: Auxiliary clock. The ACLK is the LFXT 1 CLK clock source. ACLK is software selectable for individual peripheral modules. ACLK/n: Buffered output of the ACLK. The ACLK/n is ACLK divided by 1, 2, 4 or 8 and only used externally. MCLK: Master clock. MCLK is software selectable as LFXT 1 CLK, XT 2 CLK (if available), or DCOCLK. MCLK can be divided by 1, 2, 4, or 8 within the FLL block. MCLK is used by the CPU and system. SMCLK: Sub-main clock. SMCLK is software selectable as XT 2 CLK (if available), or DCOCLK. SMCLK is software selectable for individual peripheral modules. CPE 323 51
FLL+ Clock Module Operation n n After a PUC, MCLK and SMCLK are sourced from DCOCLK at 32 times the ACLK frequency. When a 32, 768 -Hz crystal is used for ACLK, MCLK and SMCLK will stabilize to 1. 048576 MHz. Status register control bits SCG 0, SCG 1, OSCOFF, and CPUOFF configure the MSP 430 operating modes and enable or disable components of the FLL+ clock module. The SCFQCTL, SCFI 0, SCFI 1, FLL_CTL 0, and FLL_CTL 1 registers configure the FLL+ clock module. The FLL+ can be configured or reconfigured by software at any time during program execution. Example, MCLK = 64 × ACLK = 2097152 BIC #GIE, SR ; Disable interrupts MOV. B #(64− 1), &SCFQTL ; MCLK = 64 * ACLK, DCOPLUS=0 MOV. B #FN_2, &SCFIO ; Select DCO range BIS #GIE, SR ; Enable interrupts CPE 323 52
LFXT 1 Oscillator n n Low-frequency (LF) mode (XTS_FLL=0) with 32, 768 Hz watch crystal connected to XIN and XOUT High-frequency (HF) mode (XTS_FLL=1) with highfrequency crystals or resonators connected to XIN and XOUT (~450 KHz to 8 MHz) XCPx. PF bits configure the internally provided load capacitance for the LFXT 1 crystal (1, 6, 8, or 10 p. F) OSCOFF bit can be set to disable LFXT 1 CPE 323 53
XT 2 Oscillator n n XT 2 sources XT 2 CLK and its characteristics are identical to LFXT 1 in HF mode, except it does not have internal load capacitors (must be provided externally) XT 2 OFF bit disables the XT 2 oscillator if XT 2 CLK is not used for MCLK and SMCLK CPE 323 54
DCO n n n Integrated ring oscillator with RC-type characteristics DCO frequency is stabilized by the FLL to a multiple of ACLK as defined by N (the lowest 7 bits of the SCFQCTL register) DCOPLUS bit sets the f. DCOCLK to f. DCO or f. DCO/D (divider). The FLLDx bits define the divider D to 1, 2, 4 or 8. By default DCOPLUS=0 and D=2, providing f. DCOCLK= f. DCO/2 DCOPLUS = 0: f. DCOCLK = (N + 1) x f. ACLK DCOPLUS = 1: f. DCOCLK = D x (N + 1) x f. ACLK CPE 323 55
DCO Frequency Range CPE 323 56
Frequency Locked Loop n n n FLL continuously counts up or down a 10 -bit frequency integrator. The output of the frequency integrator that drives the DCO can be read in SCFI 1 and SCFI 0. The count is adjusted +1 or − 1 with each ACLK crystal period. Five of the integrator bits, SCFI 1 bits 7 -3, set the DCO frequency tap. Twenty-nine taps are implemented for the DCO (28, 29, 30, and 31 are equivalent), and each is approximately 10% higher than the previous. The modulator mixes two adjacent DCO frequencies to produce fractional taps. SCFI 1 bits 2 -0 and SCFI 0 bits 1 -0 are used for the modulator. The DCO starts at the lowest tap after a PUC or when SCFI 0 and SCFI 1 are cleared. Time must be allowed for the DCO to settle on the proper tap for normal operation. 32 ACLK cycles are required between taps requiring a worst case of 28 x 32 ACLK cycles for the DCO to settle CPE 323 57
FLL+ Clock Module Registers CPE 323 58
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