CPE 323 Introduction to Embedded Computer Systems Digital

CPE 323 Introduction to Embedded Computer Systems: Digital I/O, Watchdog Timer, Timer A Instructor: Dr Aleksandar Milenkovic Lecture Notes CPE 323

MSP 430: Digital I/O (Chapter 7 in textbook) CPE 323

Digital Input, Output n Digital inputs – they are either on or off n n n Digital outputs – set them on or off n n n Inputs from humans or sensors E. g. , switches, sensors (e. g. , door is locked, button is pressed, . . . ) Light-emitting diodes (LEDs), seven segment displays, liquid-crystal displays (LCDs) MSP 430 can supply these directly if they work from the same voltage and draw a sufficiently small current Digital input/output ports (P 1 – Pn), n=2. . . 10 n n Almost all pins can be used either for digital I/O or for other (special) functions Their operation must be configured on start up CPE 323 3

Parallel Ports Port 1 Port 2 Port 3 … Port 6 Function Select Register Px. SEL yes Interrupt Edge Select Register Px. IES yes no Interrupt Enable Register Px. IE yes no Interrupt Flag Register Px. IFG yes no Direction Register Px. DIR yes Output Register Px. OUT yes yes Input Register Px. IN P 1. P 2. P 3. 7 6 5 4 3 2 1 0 P 4. P 5. P 6. CPE 323 4

Digital I/O Introduction n n MSP 430 F 14 x – all 6 ports implemented Ports P 1 and P 2 have interrupt capability Each interrupt for the P 1 and P 2 input lines can be individually enabled and configured to provide an interrupt on a rising edge or falling edge of an input signal. The digital I/O features include: n n n Independently programmable individual I/Os Any combination of input or output Individually configurable P 1 and P 2 interrupts Independent input and output data registers The digital I/O is configured with user software CPE 323 5

Digital I/O Registers Operation n Input Register Pn. IN n Each bit in each Pn. IN register reflects the value of the input signal at the corresponding I/O pin when the pin is configured as I/O function. n n n Bit = 0: The input is low Bit = 1: The input is high Do not write to Px. IN. It will result in increased current consumption Output Registers Pn. OUT n Each bit in each Pn. OUT register is the value to be output on the corresponding I/O pin when the pin is configured as I/O function and output direction. n n Bit = 0: The output is low Bit = 1: The output is high CPE 323 6

Digital I/O Operation n Direction Registers Pn. DIR n n n Bit = 0: The port pin is switched to input direction Bit = 1: The port pin is switched to output direction Function Select Registers Pn. SEL n Port pins are often multiplexed with other peripheral module functions. n n Bit = 0: I/O Function is selected for the pin Bit = 1: Peripheral module function is selected for the pin CPE 323 7

Digital I/O Operation n Interrupt Flag Registers P 1 IFG, P 2 IFG (only for P 1 and P 2) n n Only transitions, not static levels, cause interrupts Interrupt Edge Select Registers P 1 IES, P 2 IES n n Bit = 0: No interrupt is pending Bit = 1: An interrupt is pending (only for P 1 and P 2) Each Pn. IES bit selects the interrupt edge for the corresponding I/O pin. n n Bit = 0: The Pn. IFGx flag is set with a low-to-high transition Bit = 1: The Pn. IFGx flag is set with a high-to-low transition CPE 323 8

Configuring Unused Pins n Unused pins must never be left unconnected in their default state as inputs n n Floating (unconnected) input – both pull-up and pulldown may be on causing shoot-through current => deplete your power source What should you do? n n n Wire unused pins externally to VGND or VDD and configure them as inputs (Warning: if you accidentally configure them as outputs you may damage the chip) Leave the pins unconnected externally, but connect them internally to VGND or VDD (applicable only to MSP 430 F 2 xx devices) Leave the pins unconnected and configure them as outputs (Warning: do not short circuit them with the probe) CPE 323 9

MSP 430: Watchdog Timer CPE 323

Watchdog Timer General The primary function of the watchdog-timer module (WDT) is to perform a controlled-system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can work as an interval timer, to generate an interrupt after the selected time interval. Features of the Watchdog Timer include: Ø Eight software-selectable time intervals Ø Two operating modes: as watchdog or interval timer Ø Expiration of the time interval in watchdog mode, which generates a system reset; or in timer mode, which generates an interrupt request Ø Safeguards which ensure that writing to the WDT control register is only possible using a password Ø Support of ultralow-power using the hold mode Watchdog/Timer two functions: Ø SW Watchdog Mode Ø Interval Timer Mode CPE 323 11

Watchdog Timer-Diagram CPE 323 12

Watchdog Timer-Registers q q Watchdog Timer Counter The watchdog-timer counter (WDTCNT) is a 16 -bit up-counter that is not directly accessible by software. The WDTCNT is controlled through the watchdog-timer control register (WDTCTL), which is a 16 bit read/write register located at the low byte of word address 0120 h. Any read or write access must be done using word instructions with no suffix or. w suffix. In both operating modes (watchdog or timer), it is only possible to write to WDTCTL using the correct password. Watchdog Timer Control Register WDTCTL 0120 h MDB, High. Byte Password Compare Read: High. Byte is 069 h R/W EQU MDB, Low. Byte 7 HOLD Write: High. Byte is 05 Ah, otherwise security key is violated NMIES NMI TMSEL CNTCL SSEL 0 IS 1 ISO WDT 16 -bit Control Register with Write Protection Bits 0, 1: Bits IS 0 and IS 1 select one of four taps from the WDTCNT, as described in following table. Assuming f crystal = 32, 768 Hz and f System = 1 MHz, the following intervals are possible: CPE 323 13

WDTCTL Bits 0, 1: Bits IS 0 and IS 1 select one of four taps from the WDTCNT, as described in following table. Assuming f crystal = 32, 768 Hz and f System = 1 MHz, the following intervals are possible: SSEL 0 0 1 0 1 1 IS 1 1 0 1 0 0 0 IS 0 1 1 0 0 1 0 Interval [ms] Table: WDTCNT Taps 0. 064 t. SMCLK × 2 6 0. 5 t. SMCLK × 2 9 1. 9 t. SMCLK × 2 6 8 t. SMCLK × 2 13 16. 0 t. ACLK × 2 9 32 t. SMCLK × 2 15 <– Value after PUC (reset) 250 t. ACLK × 2 13 1000 t. ACLK × 2 15 Bit 2: The SSEL bit selects the clock source for WDTCNT. SSEL = 0: WDTCNT is clocked by SMCLK. SSEL = 1: WDTCNT is clocked by ACLK. Bit 3: Counter clear bit. In both operating modes, writing a 1 to this bit restarts the WDTCNT at 00000 h. The value read is not defined. CPE 323 14

WDTCTL Bit 4: The TMSEL bit selects the operating mode: watchdog or timer. TMSEL = 0: Watchdog mode TMSEL = 1: Interval-timer mode Bit 5: The NMI bit selects the function of the RST/NMI input pin. It is cleared by the PUC signal. NMI = 0: The RST/NMI input works as reset input. As long as the RST/NMI pin is held low, the internal signal is active (level sensitive). NMI = 1: The RST/NMI input works as an edge-sensitive non-maskable interrupt input. Bit 6: If the NMI function is selected, this bit selects the activating edge of the RST/NMI input. It is cleared by the PUC signal. NMIES = 0: A rising edge triggers an NMI interrupt. NMIES = 1: A falling edge triggers an NMI interrupt. CAUTION: Changing the NMIES bit with software can generate an NMI interrupt. Bit 7: This bit stops the operation of the watchdog counter. The clock multiplexer is disabled and the counter stops incrementing. It holds the last value until the hold bit is reset and the operation continues. It is cleared by the PUC signal. HOLD = 0: The WDT is fully active. HOLD = 1: The clock multiplexer and counter are stopped. CPE 323 15

Watchdog Timer-Interrupt Function The Watchdog Timer (WDT) uses two bits in the SFRs for interrupt control. The WDT interrupt flag (WDTIFG) (located in IFG 1. 0, initial state is reset) The WDT interrupt enable (WDTIE) (located in IE 1. 0, initial state is reset) v When using the watchdog mode, the WDTIFG flag is used by the reset interrupt service routine to determine if the watchdog caused the device to reset. If the flag is set, then the Watchdog Timer initiated the reset condition (either by timing out or by a security key violation). If the flag is cleared, then the PUC was caused by a different source. See chapter 3 for more details on the PUC and POR signals. v When using the Watchdog Timer in interval-timer mode, the WDTIFG flag is set after the selected time interval and a watchdog interval-timer interrupt is requested. The interrupt vector address in interval-timer mode is different from that in watchdog mode. In interval-timer mode, the WDTIFG flag is reset automatically when the interrupt is serviced. v The WDTIE bit is used to enable or disable the interrupt from the Watchdog Timer when it is being used in interval-timer mode. Also, the GIE bit enables or disables the interrupt from the Watchdog Timer when it is being used in interval -timer mode. CPE 323 16

Watchdog Timer-Timer Mode v v Setting WDTCTL register bit TMSEL to 1 selects the timer mode. This mode provides periodic interrupts at the selected time interval. A time interval can also be initiated by writing a 1 to bit CNTCL in the WDTCTL register. When the WDT is configured to operate in timer mode, the WDTIFG flag is set after the selected time interval, and it requests a standard interrupt service. The WDT interrupt flag is a single-source interrupt flag and is automatically reset when it is serviced. The enable bit remains unchanged. In interval-timer mode, the WDT interrupt-enable bit and the GIE bit must be set to allow the WDT to request an interrupt. The interrupt vector address in timer mode is different from that in watchdog mode. CPE 323 17

Watchdog Timer-Examples q How to select timer mode /* WDT is clocked by f. ACLK (assumed 32 Khz) */ WDTCL=WDT_ADLY_250; // WDT 250 MS/4 INTERVAL TIMER IE 1 |=WDTIE; // ENABLE WDT INTERRUPT q How to stop watchdog timer WDTCTL=WDTPW + WDTHOLD ; q // stop watchdog timer Assembly programming WDT_key WDTStop WDT 250 . equ mov 05 A 00 h ; Key to access WDT #(WDT_Key+80 h), &WDTCTL ; Hold Watchdog #(WDT_Key+1 Dh), &WDTCTL ; WDT, 250 ms Interval CPE 323 18

MSP 430: Timer_A CPE 323

Timer_A MSP 430 x 1 xx n n n 16 -bit counter with 4 operating modes Selectable and configurable clock source Three (or five) independently configurable capture/compare registers with configurable inputs Three (or five) individually configurable output modules with 8 output modes multiple, simultaneous, timings; multiple capture/compares; multiple output waveforms such as PWM signals; and any combination of these. Interrupt capabilities n each capture/compare block individually configurable CPE 323 20

Timer_A 5 - MSP 430 x 1 xx Block Diagram Page 11 -3, User’s Manual CPE 323 21

Timer_A Counting Modes Stop/Halt Mode UP/DOWN Mode Timer counts between 0 and CCR 0 and 0 Timer is halted with the next +CLK UP Mode Continuous Mode Timer counts between 0 and CCR 0 Timer continuously counts up 0 FFFFh CCR 0 0 h CPE 323 22

Timer_A 16 -bit Counter 15 0 TACTL Input Select unused 160 h rw(0) Page 11 -12, User’s Manual rw(0) Input Divider rw(0) SSEL 1 SSEL 0 0 1 1 Mode Control rw(0) ID 1 ID 0 0 0 1 1 0 1 un. TAIE TAIFG used CLR rw(0) MC 1 MC 0 0 0 1 1 0 1 rw(0) (w)(0) rw(0) Stop Mode Up Mode Continuous Mode Up/Down Mode 1/1, Pass 1/2 1/4 1/8 TACLK MCLK INCLK CPE 323 23

Timer_A Capture Compare Blocks CMPx CCISx 1 CCISx 0 0 CCIx. A 1 CCIx. B 2 GND 3 VCC Timer Clock CCMx 0 0 Disabled 1 Pos. Edge 0 Neg. Edge 1 Both Edges 0 Capture/Compare Register CCRx Capture 0 Synchronize Capture Timer Bus Data Bus 15 1 Capture Mode CCMx 1 0 0 1 1 Overflow x COVx Logic Capture Path SCSx 15 0 Comparator to Port 0 x EQUx 0 1 Compare Path EN A CCIx CCRx 0172 h to 017 Eh CCTLx 162 h to 16 Eh 2 rw(0) CAPTURE MODE rw(0) SCCIx 0 15 rw(0) 15 Set_CCIFGx Y 15 2 CAPx rw(0) INPUT SELECT rw(0) rw(0) SCS SCCI un. CAP used rw(0) rw(0) OUTMODx rw(0) CPE 323 rw(0) rw(0) 0 CCIE CCI OUT COV CCIFG rw(0) r rw(0) 24

Timer_A Output Units Timer Clock TAx EQUx Logic OUTx (CCTLx. 2) Output EQU 0 D Set Output Signal Outx Q To Output Logic TAx Timer Clock Reset POR Output Mode 0 OUTx OMx 2 OMx 1 OMx 0 Function Operational Conditions 0 0 0 Output Mode Outx signal is set according to Outx bit 0 0 1 Set EQUx sets Outx signal clock synchronous with timer clock 0 1 0 PWM Toggle/Reset EQUx toggles Outx signal, reset with EQU 0, clock sync. with timer clock 0 1 1 PWM Set/Reset EQUx sets Outx signal, reset with EQU 0, clock synchronous with timer clock 1 0 0 Toggle EQUx toggles Outx signal, clock synchronous with timer clock 1 0 1 Reset EQUx resets Outx signal clock synchronous with timer clock 1 1 0 PWM Toggle/Reset EQUx toggles Outx signal, set with EQU 0, clock synchronous with timer clock 1 1 1 PWM Set/Reset EQUx resets Outx signal, set with EQU 0, clock synchronous with timer clock CPE 323 25

Timer_A Continuous-Mode Example 0 FFFh 0 h Px. x TA 0 Input CCR 0: Capture Mode: Positive Edge Px. y TA 1 Input CCR 1: Capture Mode: Both Edges Px. z TA 2 Input CCR 2: Capture Mode: Negative Edge CCR 0 CCR 1 CCR 1 Interrupts can be generated CCR 2 Example shows three independent HW event captures. CCRx “stamps” time of event - Continuous-Mode is ideal. CPE 323 26

Timer_A PWM Up-Mode Example 0 FFFFh CCR 0 CCR 1 CCR 2 0 h TA 1 Output CCR 1: PWM Set/Reset Px. x CCR 2: PWM Reset/Set TA 2 Output Px. y CCR 0: PWM Toggle Auto Re-load TA 0 Output Px. z EQU 0 EQU 2 EQU 1 EQU 2 EQU 0 Interrupts can be generated Output Mode 4: PWM Toggle Example shows three different asymmetric PWM-Timings generated with the Up-Mode CPE 323 27

Timer_A PWM Up/Down Mode Example 0 FFFFh thlfper CCR 0 CCR 2 CCR 1 CCR 3 0 h TA 1 Output 0 Degrees (0. 5 x. Vmotor) Px. x tpw 1 TA 2 Output +120 Degrees tpw 2 (0. 93 x. Vmotor) Px. y tpw 3 -120 Degrees TA 0 Output Px. z (0. 07 x. Vmotor) TIMOV EQU 0 TIMOV Interrupts can be generated Example shows Symmetric PWM Generation Digital Motor Control CPE 323 28

C Examples, CCR 0 Contmode ISR, TA_0 ISR //******************************** // MSP-FET 430 P 140 Demo - Timer_A Toggle P 1. 0, // CCR 0 Contmode ISR, DCO SMCLK // Description; Toggle P 1. 0 using software and TA_0 ISR. Toggle rate is // set at 50000 DCO/SMCLK cycles. Default DCO frequency used for TACLK. // Durring the TA_0 ISR P 0. 1 is toggled and 50000 clock cycles are added to // CCR 0. TA_0 ISR is triggered exactly 50000 cycles. CPU is normally off and // used only durring TA_ISR. // ACLK = n/a, MCLK = SMCLK = TACLK = DCO~ 800 k // // // MSP 430 F 149 // -------// /|| XIN|// | | | // --|RST XOUT|// | | // | P 1. 0|-->LED // // M. Buccini // Texas Instruments, Inc // September 2003 // Built with IAR Embedded Workbench Version: 1. 26 B // December 2003 // Updated for IAR Embedded Workbench Version: 2. 21 B //*********************************** #include <msp 430 x 14 x. h> void main(void) { WDTCTL = WDTPW + WDTHOLD; // Stop WDT P 1 DIR |= 0 x 01; // P 1. 0 output CCTL 0 = CCIE; // CCR 0 interrupt enabled CCR 0 = 50000; TACTL = TASSEL_2 + MC_2; // SMCLK, contmode _BIS_SR(LPM 0_bits + GIE); // Enter LPM 0 w/ interrupt } // Timer A 0 interrupt service routine interrupt[TIMERA 0_VECTOR] void Timer. A(void) { P 1 OUT ^= 0 x 01; // Toggle P 1. 0 CCR 0 += 50000; // Add Offset to CCR 0 } CPE 323 29

C Examples, CCR 0 Upmode ISR, TA_0 //************************************ #include <msp 430 x 14 x. h> // MSP-FET 430 P 140 Demo - Timer_A Toggle P 1. 0, CCR 0 upmode ISR, 32 k. Hz ACLK // void main(void) // Description; Toggle P 1. 0 using software and the TA_0 ISR. Timer_A is { // configured in an upmode, thus the timer will overflow when TAR counts WDTCTL = WDTPW + WDTHOLD; // Stop WDT // to CCR 0. In this example, CCR 0 is loaded with 1000 -1. P 1 DIR |= 0 x 01; // P 1. 0 output // Toggle rate = 32768/(2*1000) = 16. 384 CCTL 0 = CCIE; // CCR 0 interrupt enabled // ACLK = TACLK = 32768, MCLK = SMCLK = DCO~ 800 k CCR 0 = 1000 -1; // //*An external watch crystal on XIN XOUT is required for ACLK*// TACTL = TASSEL_1 + MC_1; // ACLK, upmode // _BIS_SR(LPM 3_bits + GIE); // Enter LPM 3 w/ // MSP 430 F 149 interrupt // -------} // /|| XIN|// | | | 32 k. Hz // --|RST XOUT|// Timer A 0 interrupt service routine // | | #pragma vector=TIMERA 0_VECTOR // | P 1. 0|-->LED Interrupt[TIMERA 0_VECTOR] void Timer_A (void) // { // M. Buccini P 1 OUT ^= 0 x 01; // Toggle P 1. 0 // Texas Instruments, Inc } // October 2003 // Built with IAR Embedded Workbench Version: 1. 26 B // December 2003 // Updated for IAR Embedded Workbench Version: 2. 21 B //************************************ CPE 323 30

C Examples, CCR 1 Contmode ISR, TA_1 //********************************* // MSP-FET 430 P 140 Demo – // Timer_A Toggle P 1. 0, CCR 1 Contmode ISR, CO SMCLK // Description; Toggle P 1. 0 using software and TA_1 ISR. // Toggle rate is set at 50000 DCO/SMCLK cycles. // Default DCO frequency used for TACLK. // Durring the TA_1 ISR P 0. 1 is toggled and // 50000 clock cycles are added to CCR 1. // TA_1 ISR is triggered exactly 50000 cycles. // CPU is normally off and used only durring TA_ISR. // ACLK = n/a, MCLK = SMCLK = TACLK = DCO ~ 800 k // Proper use of TAIV interrupt vector generator demonstrated. // // MSP 430 F 149 // -------// /|| XIN|// | | | // --|RST XOUT|// | | // | P 1. 0|-->LED // // M. Buccini // Texas Instruments, Inc // September 2003 // Built with IAR Embedded Workbench Version: 1. 26 B // December 2003 // Updated for IAR Embedded Workbench Version: 2. 21 B //******************************* CPE 323 #include <msp 430 x 14 x. h> void main(void) { WDTCTL = WDTPW + WDTHOLD; // Stop WDT P 1 DIR |= 0 x 01; // P 1. 0 output CCTL 1 = CCIE; // CCR 1 interrupt enabled CCR 1 = 50000; TACTL = TASSEL_2 + MC_2; // SMCLK, Contmode _BIS_SR(LPM 0_bits + GIE); // Enter LPM 0 w/ interrupt } // Timer_A 3 Interrupt Vector (TAIV) handler #pragma vector=TIMERA 1_VECTOR __interrupt void Timer_A(void) { switch( TAIV ) { case 2: // CCR 1 { P 1 OUT ^= 0 x 01; // Toggle P 1. 0 CCR 1 += 50000; // Add Offset to CCR 1 } break; case 4: break; // CCR 2 not used case 10: break; // overflow not used } } 31

C Examples, PWM, TA 1 -2 upmode //************************************** // MSP-FET 430 P 140 Demo - Timer_a PWM TA 1 -2 upmode, DCO SMCLK // // Description; This program will generate a two PWM outputs on P 1. 2/1. 3 using // Timer_A in an upmode. The value in CCR 0, defines the period and the // values in CCR 1 and CCR 2 the duty PWM cycles. Using ~ 800 k. Hz SMCLK as TACLK, // the timer period is ~ 640 us with a 75% duty cycle on P 1. 2 and 25% on P 1. 3. // ACLK = na, SMCLK = TACLK = default DCO ~ 800 k. Hz. // // MSP 430 F 149 // --------// /|| XIN|void main(void) // | | | // --|RST XOUT|{ // | | WDTCTL = WDTPW + WDTHOLD; // Stop WDT // | P 1. 2|--> CCR 1 - 75% PWM P 1 DIR |= 0 x 0 C; // P 1. 2 and P 1. 3 output // | P 1. 3|--> CCR 2 - 25% PWM // P 1 SEL |= 0 x 0 C; // P 1. 2 and P 1. 3 TA 1/2 options // M. Buccini CCR 0 = 512 -1; // PWM Period // Texas Instruments, Inc CCTL 1 = OUTMOD_7; // CCR 1 reset/set // September 2003 // Built with IAR Embedded Workbench Version: 1. 26 B CCR 1 = 384; // CCR 1 PWM duty cycle // January 2004 CCTL 2 = OUTMOD_7; // CCR 2 reset/set // Updated for IAR Embedded Workbench Version: 2. 21 B CCR 2 = 128; // CCR 2 PWM duty cycle //*************************** TACTL = TASSEL_2 + MC_1; _BIS_SR(LPM 0_bits); // SMCLK, up mode // Enter LPM 0 } CPE 323 32