Course WrapUp Miodrag Bolic CEG 4136 What was

Course Wrap-Up Miodrag Bolic CEG 4136

What was covered • • • Interconnection network topologies and performance Shared-memory architectures Message passing architectures Scheduling Multicores and networks on chip Cloud computing • Elements of system-on-chip design in Labs and sometimes during lectures • Basic elements of parallel programming

What was not covered • Parallel programming • Operating systems • Advanced manycore architectures

Final Format • Duration: 3 hours • Format: – 1 theoretical problem – 4 problems with multiple parts

Final Format • Closed book, closed notes exam. • No cheat sheet • Only material cover in the class, DGDs, assignments and labs will be on the exam.

Complaining • You can come to see the exam on – Fri (Dec 23 rd) 13: 00 -14: 00 • To complain: you will fill the form and I will notify you about the decision.

Things to Review • Assignments • Lecture notes • Quizzes from 2005, 2006 and 2007

Format 1. 2. 3. 4 5 Theoretical question Interconnection networks Message passing and scheduling Shared memory systems Advanced architectures or scheduling

Example of theoretical question for final Type of questions: • Compare • Define and explain What to study: • Everything

Dynamic Interconnection Networks • Properties – Network latency – Hardware complexity – Blocking/Nonblocking • Switches – Permutations and legitimate states • Multistage Interconnection networks – Omega network: » topology, » number of switches, stages and permutations, » routing protocol • Crossbar

Static Interconnection Networks • Network properties – Node degree d – Diameter D – Bisection width • • Complete Star Tree Linear array Ring Mesh Torus Hypercube – routing protocol • k-ary n-cubes • To prepare for dynamic and static interconnection networks use – slides, – assignment and

Message passing • Message Passing Properties • • • Store-and-forward routing Wormhole routing Virtual channels Deterministic routing algorithms Deadlocks

Scheduling • Dependence graph • Scheduling without considering communication – Scheduling inforest/outforest task graphs • Heuristic algorithms – Communication Delay versus Parallelism – Clustering – Node duplication

Shared Memory Systems • Cache coherence policies – Snooping protocols – Directory protocols

Parallel programing • Parallel addition and matrix multiplication on shared memory and message passing systems • Again – you will be required to modify the given program

Performance • • • Amdahl law Speedup, Efficiency Parallelism profile, average parallelism, MIPS Scalability Understanding of performance of the program for parallel addition • Classification of parallel processing systems

Embedded multicores • Review terminology – – – Symmetric and Asymetric processing Virtualization and hypervisor Cache stashing Run to completion Posix and Open. MP • Example of router implementation using processor cores

Cache coherence for manycores • Coherence Bandwidth Requirements • Broadcast vs. Directory Protocols • Read hit and read miss procedure for: – Private L 2 caches – Shared L 2 caches

Router design for manycores • Architecture of the virtual channel router • Pipeline stages – Lookahead routing • Buffer Organization • Switch organization • Arbiters and allocators – Round-robin arbiter

Cloud computing • • Terminology Services Advantages Comparison with grid and high-performance computing