COSC 3406 Computer Organization Lecture 3 Computer Abstraction

COSC 3406: Computer Organization Lecture 3: Computer Abstraction Kalpdrum Passi Fall 2016 ( www. cs. laurentian. ca/kpassi/cosc 3406. html )

Chapter 1 Computer Abstractions and Technology

Instruction Count and CPI ° Instruction Count for a program • Determined by program, ISA and compiler ° Average cycles per instruction • Determined by CPU hardware • If different instructions have different CPI - Average CPI affected by instruction mix

CPI Example ° Computer A: Cycle Time = 250 ps, CPI = 2. 0 ° Computer B: Cycle Time = 500 ps, CPI = 1. 2 ° Same ISA ° Which is faster, and by how much? A is faster… …by this much

CPI in More Detail ° If different instruction classes take different numbers of cycles n Weighted average CPI Relative frequency

CPI Example ° Alternative compiled code sequences using instructions in classes A, B, C n Class A B C CPI for class 1 2 3 IC in sequence 1 2 IC in sequence 2 4 1 1 Sequence 1: IC = 5 n n Clock Cycles = 2× 1 + 1× 2 + 2× 3 = 10 Avg. CPI = 10/5 = 2. 0 n Sequence 2: IC = 6 n n Clock Cycles = 4× 1 + 1× 2 + 1× 3 =9 Avg. CPI = 9/6 = 1. 5

Performance Summary The BIG Picture ° Performance depends on • Algorithm: affects IC, possibly CPI • Programming language: affects IC, CPI • Compiler: affects IC, CPI • Instruction set architecture: affects IC, CPI, Tc

° Power provides a limit to what we can cool, ° In the post-PC era the really valuable resource is energy. ° Dominant technology for IC is CMOS (complementary metal oxide semiconductor) § 1. 7 The Power Wall Power Trends

Power Trends ° The primary source of energy consumption is so-called dynamic energy—that is, energy that is consumed when transistors switch states from 0 to 1 and vice versa. ° The dynamic energy depends on the capacitive loading of each transistor and the voltage applied: ° This equation is the energy of a pulse during the logic transition of 0 → 1 → 0 or 1 → 0 → 1. ° The power required per transistor is just the product of energy of a transition and the frequency of transitions: × 30 5 V → 1 V × 1000

Reducing Power ° Suppose a new CPU has • 85% of capacitive load of old CPU • 15% voltage and 15% frequency reduction n The power wall n n n We can’t reduce voltage further We can’t remove more heat How else can we improve performance?

Constrained by power, instruction-level parallelism, memory latency § 1. 8 The Sea Change: The Switch to Multiprocessors Uniprocessor Performance

Multiprocessors ° Multicore microprocessors • More than one processor per chip ° Requires explicitly parallel programming • Compare with instruction level parallelism - Hardware executes multiple instructions at once - Hidden from the programmer • Hard to do - Programming for performance - Load balancing - Optimizing communication and synchronization

SPEC CPU Benchmark ° Programs used to measure performance • Supposedly typical of actual workload ° System Performance Evaluation Cooperative (SPEC) • Develops benchmarks for CPU, I/O, Web, … ° SPEC CPU 2006 • Elapsed time to execute a selection of programs - Negligible I/O, so focuses on CPU performance • Dividing the execution time of a reference processor by the execution time of the evaluated computer normalizes the execution time measurements; • This normalization yields a measure, called the SPECratio • SPECratio is the inverse of execution time.

CINT 2006 for Intel Core i 7 920 o A CINT 2006 (integer) or CFP 2006 (floating-point) Summary measurement is obtained by taking the geometric mean of SPECratios

SPEC Power Benchmark ° Power consumption of servers at different workload levels, divided into 10% increments, over a period of time. ° SPECpower started with another SPEC benchmark for Java business applications (SPECJBB 2005), ° It exercises the processors, caches, and main memory as well as the Java virtual machine, compiler, garbage collector, and pieces of the operating system. ° Performance is measured in throughput, and the units are business operations per second. • where ssj_opsi is performance at each 10% increment and poweri is power consumed at each performance level • Power: Watts (Joules/sec)

SPECpower_ssj 2008 for Xeon X 5650

° Improving an aspect of a computer and expecting a proportional improvement in overall performance n Example: multiply accounts for 80 s/100 s n How much improvement in multiply performance to get 5× overall? n n Can’t be done! Corollary: make the common case fast § 1. 10 Fallacies and Pitfalls Pitfall: Amdahl’s Law

Fallacy: Low Power at Idle ° Look back at i 7 power benchmark • At 100% load: 258 W • At 50% load: 170 W (66%) • At 10% load: 121 W (47%) ° Google data center • Mostly operates at 10% – 50% load • At 100% load less than 1% of the time ° Consider designing processors to make power proportional to load ° If future servers used, say, 10% of peak power at 10% workload, we could reduce the electricity bill of datacenters

Fallacy: Designing for performance and designing for energy efficiency unrelated ° Energy is power over time ° Hardware or software optimizations that take less time save energy overall even if the optimization takes a bit more energy when it is used.

Pitfall: MIPS as a Performance Metric ° MIPS: Millions of Instructions Per Second • Doesn’t account for - Differences in ISAs between computers - Differences in complexity between instructions n CPI varies between programs on a given CPU and so does MIPS

° Cost/performance is improving • Due to underlying technology development ° Hierarchical layers of abstraction • In both hardware and software § 1. 9 Concluding Remarks ° Instruction set architecture • The hardware/software interface ° Execution time: the best performance measure ° Individually the factors do not determine performance: only the product, is a reliable measure of performance.

Concluding Remarks ° Two of the key ideas are • exploiting parallelism in the program, via multiple processors, and • exploiting locality of accesses to a memory hierarchy, typically via caches. ° Power is a limiting factor • Use parallelism to improve performance ° Computer designs measured by cost and performance, as well as • energy, dependability, cost of ownership, and scalability.

Chapter 2 Instructions: Language of the Computer

° The repertoire of instructions of a computer ° Different computers have different instruction sets • But with many aspects in common ° Early computers had very simple instruction sets • Simplified implementation ° Many modern computers also have simple instruction sets § 2. 1 Introduction Instruction Set

The ARMv 8 Instruction Set ° A subset, called LEGv 8, used as the example throughout the book ° Commercialized by ARM Holdings (www. arm. com) ° Large share of embedded core market • Applications in consumer electronics, network/storage equipment, cameras, printers, … ° Typical of many modern ISAs • See ARM Reference Data tear-out card

° Add and subtract, three operands • Two sources and one destination ADD a, b, c // a gets b + c ° All arithmetic operations have this form ° Each LEGv 8 arithmetic instruction performs only one operation and must always have exactly three variables ° Design Principle 1: Simplicity favours regularity • Regularity makes implementation simpler • Simplicity enables higher performance at lower cost § 2. 2 Operations of the Computer Hardware Arithmetic Operations

Arithmetic Example ° Compiling Two C Assignment Statements into LEGv 8: a = b +c ; d=a–e; ° Compiled LEGv 8 code: ADD a, b, c SUB d, a, e ° Compiling a Complex C Assignment into LEGv 8: f = (g + h) - (i + j); ° Compiled LEGv 8 code: ADD t 0, g, h ADD t 1, i, j SUB f, t 0, t 1 // temp t 0 = g + h // temp t 1 = i + j // f = t 0 - t 1