COP 3402 Systems Software Euripides Montagne University of

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COP 3402 Systems Software Euripides Montagne University of Central Florida (Fall 2007) Eurípides Montagne

COP 3402 Systems Software Euripides Montagne University of Central Florida (Fall 2007) Eurípides Montagne University of Central Florida

COP 3402 Systems Software 2 The. Lecture processor as an instruction interpreter Eurípides Montagne

COP 3402 Systems Software 2 The. Lecture processor as an instruction interpreter Eurípides Montagne University of Central Florida

Outline 1. The structure of a tiny computer. 2. A program as an isolated

Outline 1. The structure of a tiny computer. 2. A program as an isolated system. 3. The instruction format 4. Assembly language Eurípides Montagne University of Central Florida 3

Von-Neumann Machine (VN) IP MAR MEMORY IR OP ADDRESS MDR A Decoder ALU Eurípides

Von-Neumann Machine (VN) IP MAR MEMORY IR OP ADDRESS MDR A Decoder ALU Eurípides Montagne University of Central Florida 4

Instruction Cycle • Instruction cycle, or machine cycle, in VN is composed of 2

Instruction Cycle • Instruction cycle, or machine cycle, in VN is composed of 2 steps: • 1. Fetch Cycle: instructions are retrieved from memory • 2. Execution Cycle: instructions are executed • A hardware description language will be used to understand how instructions are executed in VN Eurípides Montagne University of Central Florida 5

Definitions • IP: Instruction Pointer (a. k. a. PC) is a register that holds

Definitions • IP: Instruction Pointer (a. k. a. PC) is a register that holds the address of the next instruction to be executed. • MAR: Memory Address Register is used to locate a specific memory location to read (load) or write (store) its content. • MEM: Main storage or RAM (Random Access Memory) and is used to store programs and data. Eurípides Montagne University of Central Florida 6

Definitions • MDR: Memory Data Register register used to receive the content of the

Definitions • MDR: Memory Data Register register used to receive the content of the memory location addressed by MAR or to store a value in a memory location addressed by MAR. This register receives either instructions or data from memory • IR: Instruction Register is used to store instructions Eurípides Montagne University of Central Florida 7

Definition • DECODER: Depending on the value of the IR, this device will send

Definition • DECODER: Depending on the value of the IR, this device will send signals through the appropriate wires to execute an instruction. • A: Accumulator is used to store data to be used as input to the ALU. • ALU: Arithmetic Logic Unit is used to execute mathematical instructions such as ADD or SUB Eurípides Montagne University of Central Florida 8

Fetch-Execute Cycle • In VN, the instruction cycle is given by the following loop:

Fetch-Execute Cycle • In VN, the instruction cycle is given by the following loop: Fetch Execute • In order to explain further details about the fetch, the data movements along different paths can be described in 4 steps. Eurípides Montagne University of Central Florida 9

Data Movement 1 • Given register IP and MAR the transfer of the contents

Data Movement 1 • Given register IP and MAR the transfer of the contents of IP into MAR is indicated as : MAR IP IP MAR MEMORY OP ADDRESS MDR A Decoder ALU Eurípides Montagne University of Central Florida 10

Data Movement 2 • To transfer information from a memory location to the register

Data Movement 2 • To transfer information from a memory location to the register MDR, we use: IP MAR MEMORY MAR MDR MEM[MAR] • The address of the memory location has been stored previously into the MAR register Eurípides Montagne OP ADDRESS MDR A Decoder University of Central Florida ALU 11

Data Movement 3 • To transfer information from the MDR register to a memory

Data Movement 3 • To transfer information from the MDR register to a memory location, we use: MEM [MAR] MDR *see previous slide for diagram • The address of the memory location has been previously stored into the MAR Eurípides Montagne University of Central Florida 12

Instruction Register Properties • The Instruction Register (IR) has two fields: Operation (OP) and

Instruction Register Properties • The Instruction Register (IR) has two fields: Operation (OP) and the ADDRESS. • These fields can be accessed using the selector operator “. ” Eurípides Montagne University of Central Florida 13

Data Movement 4 • The Operation portion of the field is accessed as IR.

Data Movement 4 • The Operation portion of the field is accessed as IR. OP • The operation field of the IR register is sent out to the DECODER using: DECODER IR. OP • DECODER: If the value of IR. OP==00, then the decoder can be set to execute the fetch cycle again. Eurípides Montagne University of Central Florida 14

Data Movement 4 Cont. DECODER IR. OP IP MAR MEMORY OP ADDRESS MDR A

Data Movement 4 Cont. DECODER IR. OP IP MAR MEMORY OP ADDRESS MDR A Decoder ALU Eurípides Montagne University of Central Florida 15

Instruction Cycle • The instruction cycle has 2 components. • Fetch cycle retrieves the

Instruction Cycle • The instruction cycle has 2 components. • Fetch cycle retrieves the instruction from memory. • Execution cycle carries out the instruction loaded previously. Eurípides Montagne University of Central Florida 16

00 Fetch Cycle 1. MAR IP 2. MDR MEM[MAR] 3. IR MDR 4. IP

00 Fetch Cycle 1. MAR IP 2. MDR MEM[MAR] 3. IR MDR 4. IP IP+1 5. DECODER IR. OP Eurípides Montagne 1. Copy contents of IP into MAR 2. Load content of memory location into MDR 3. Copy value stored in MDR into IR 4. Increment IP register 5. Select Instruction to be executed University of Central Florida 17

Execution: 01 LOAD 1. 2. 3. 4. MAR IR. ADDR MEM[MAR] A MDR DECODER

Execution: 01 LOAD 1. 2. 3. 4. MAR IR. ADDR MEM[MAR] A MDR DECODER 00 Eurípides Montagne 1. Copy the IR address value field into MAR 2. Load the content of a memory location into MDR 3. Copy content of MDR into A register 4. Set Decoder to execute Fetch Cycle University of Central Florida 18

Execution: 02 ADD 1. 2. 3. 4. MAR IR. ADDR MEM[MAR] A A +

Execution: 02 ADD 1. 2. 3. 4. MAR IR. ADDR MEM[MAR] A A + MDR DECODER 00 Eurípides Montagne 1. Copy the IR address value field into MAR 2. Load content of memory location to MDR 3. Add contents of MDR and A register and store result into A 4. Set Decoder to execute Fetch cycle University of Central Florida 19

Execution: 03 STORE 1. 2. 3. 4. MAR IR. ADDR MDR A MEM[MAR] MDR

Execution: 03 STORE 1. 2. 3. 4. MAR IR. ADDR MDR A MEM[MAR] MDR DECODER 00 Eurípides Montagne 1. Copy the IR address value field into MAR 2. Copy A register contents into MDR 3. Copy content of MDR into a memory location 4. Set Decoder to execute fetch cycle University of Central Florida 20

Execution: 07 HALT 1. STOP Eurípides Montagne 1. Program ends normally University of Central

Execution: 07 HALT 1. STOP Eurípides Montagne 1. Program ends normally University of Central Florida 21

Instruction Set Architecture (ISA) 00 Fetch (hidden instruction) MAR IP MDR MEM[MAR] IR MDR

Instruction Set Architecture (ISA) 00 Fetch (hidden instruction) MAR IP MDR MEM[MAR] IR MDR IP IP+1 DECODER IR. OP 02 Add MAR IR. Address MDR MEM[MAR] A A + MDR DECODER 00 Eurípides Montagne 01 Load MAR IR. Address MDR MEM[MAR] A MDR DECODER 00 03 Store MAR IR. Address MDR A MEM[MAR] MDR DECODER 00 07 Halt University of Central Florida 22

One Address Architecture (instruction format) • The instruction format of this one-address architecture is:

One Address Architecture (instruction format) • The instruction format of this one-address architecture is: OP LOAD Eurípides Montagne ADDRESS 0000 000 A University of Central Florida 23

Instruction Set Architecture • 01 - LOAD <X> Loads the contents of memory location

Instruction Set Architecture • 01 - LOAD <X> Loads the contents of memory location “X” into A (A stand for Accumulator). • 02 - ADD <X> The data value stored at address “X” is added to the A and the result is stored back in the A. • 03 - STORE <X> Store the contents of A into memory location “X”. • 04 - SUB <X> Subtracts the value located at address “X” from the A and stored the result back in the A. Eurípides Montagne University of Central Florida 24

Instruction Set Architecture • 05 - IN <Device # > A value from the

Instruction Set Architecture • 05 - IN <Device # > A value from the input device is transferred into the AC. • 06 - OUT <Device #> Print out the contents of the AC in the output device. • Device # 5 7 9 Device Keyboard Printer Screen For instance you can write: 003 IN <5> “ 23” where “ 23” is the value you are typing in. Eurípides Montagne University of Central Florida 25

Instruction Set Architecture • 07 - Halt The machine stops execution of the program.

Instruction Set Architecture • 07 - Halt The machine stops execution of the program. (Return to the O. S) • 08 - JMP <X> Causes an unconditional branch to address “X”. IP X • 09 - SKIPZ If the contents of Z flag = 1 the next instruction is skipped. (If the output of the ALU equals zero the Z flag is set to 1. In this machine it means Accumulator = 0) Eurípides Montagne University of Central Florida 26

If the output of the ALU equals zero the Z flag is set to

If the output of the ALU equals zero the Z flag is set to 1 IP MAR MEMORY Z =Condition Code OP ADDRESS MDR A 0 Decoder ALU A=0 Z Eurípides Montagne University of Central Florida 27

Instruction Set Architecture • For this tiny assembly language we are using only one

Instruction Set Architecture • For this tiny assembly language we are using only one condition code (CC) Z = 0. • Condition codes indicates the result of the most recent arithmetic operation • Two more flags (CC) can be incorporated to test negative and positives values: G = 1 Positive value Z = 1 Zero L = 1 Negative value Eurípides Montagne University of Central Florida 28

Program State Word (condition codes - CC) The PSW is a register in the

Program State Word (condition codes - CC) The PSW is a register in the CPU that provides the OS with information on the status of the running program Interrupt Flags IP MASK CC Mode OV MP PI TI I/O SVC To be defined later G Z L In addition to the Z flag we can incorporate two more flags: 1) G meaning “greater than zero” 2) L meaning “less than zero” Eurípides Montagne University of Central Florida 29

ISA Instruction descriptions opcode mnemonic meaning 0001 0010 0011 0100 0101 0110 0111 1000

ISA Instruction descriptions opcode mnemonic meaning 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 0011 LOAD <x> ADD <x> STORE <x> SUB <x> IN <Device_#> OUT <Device_#> HALT JMP <x> SKIPZ SKIPP SKIPN A Mem[x] A A + Mem[x] A A A – Mem[x] A read from Device A output to Device Stop PC x If Z = 1 Skip next instruction If P = 1 Skip next instruction If N = 0 Skip next instruction Eurípides Montagne University of Central Florida 30

Assembly language Programming examples Assign a memory location to each variable: C X +

Assembly language Programming examples Assign a memory location to each variable: C X + Y; <000> <001> <002> If necessary to use temporary memory locations, assign labels (names) to them. Eurípides Montagne University of Central Florida 31

Assembly language Programming examples Memory 000 1245 001 1755 002 0000 After execution 003

Assembly language Programming examples Memory 000 1245 001 1755 002 0000 After execution 003 Load <000> 004 Add <001> 005 Store <002> 006 Halt Eurípides Montagne University of Central Florida Memory 000 1245 001 1755 002 3000 003 Load <000> 004 Add <001> 005 Store <002> 006 Halt 32

One Address Architecture • The instruction format of this one-address architecture consists of 16

One Address Architecture • The instruction format of this one-address architecture consists of 16 bits: 4 bits to represent instructions and 12 bits for addresses : OP 0001 Eurípides Montagne ADDRESS 0000 0001 University of Central Florida 33

Assembler: translate Symbolic code to object code(binary) Assembly Language 003 Load <000> 004 Add

Assembler: translate Symbolic code to object code(binary) Assembly Language 003 Load <000> 004 Add <001> 005 Store <002> 006 End Assembler Eurípides Montagne 01 LOAD 02 ADD 03 STORE 04 SUB 05 IN 003 004 005 006 06 OUT 07 END 08 JMP 09 SKIPZ In binary 0001 0000 0010 0000 0001 0011 00000011 0111 0000000 University of Central Florida 34

Assembler Directives • The next step to improve our assembly language is the incorporation

Assembler Directives • The next step to improve our assembly language is the incorporation of pseudo-ops (assembler directives) to invoke a special service from the assembler (pseudo-operations do not generate code). begin tell the assembler where the program starts . data to reserve a memory location. . end tells the assembler where the program ends. Labels are symbolic names used to identify memory locations. Eurípides Montagne University of Central Florida 35

Assembler Directives This is an example of the usage of assembler directives. begin “Assembly

Assembler Directives This is an example of the usage of assembler directives. begin “Assembly language instructions” halt (return to OS). data (to reserve a memory location). end ( tells the assembler where the program ends) note: the directive. end can be used to indicate where the program Starts (for eample: “. end <insert label here>” Eurípides Montagne University of Central Florida 36

Assembly language Programming examples Label start a b TWO Eurípides Montagne opcode address. begin

Assembly language Programming examples Label start a b TWO Eurípides Montagne opcode address. begin in x 005 store a in x 005 store b load a sub TWO add b out x 009 halt. data 0. data 2. end start University of Central Florida Text section (code) Data section 37

LOAD/STORE ARCHITECTURE A load /store architecture has: a “register file” in the CPU and

LOAD/STORE ARCHITECTURE A load /store architecture has: a “register file” in the CPU and it uses three instruction formats. Therefore, its assembly lenguage is different to the one of the accumulator machine ADDRESS OP OP Ri Eurípides Montagne JMP <address> ADDRESS Rj Rk University of Central Florida Load R 3, <address> Add R 3, R 2, R 4

Next time will talk about Lecture 2 virtual machines Eurípides Montagne University of Central

Next time will talk about Lecture 2 virtual machines Eurípides Montagne University of Central Florida