CONTROLLABILITY AND OBSERVABILITY KALYANA R KANTIPUDI VLSI TESTING

CONTROLLABILITY AND OBSERVABILITY KALYANA R KANTIPUDI VLSI TESTING ’ 05 TERM PAPER 4/26/05 Kantipudi: ELEC 7250 1

DEFINITIONS: n n Controllability: The difficulty of setting a particular logic signal to 0 or 1 Observability: The difficulty of observing the state of a logic signal Applicable for both combinational and sequential testability measures. Combinational Testability measures: Spatial domain Sequential Testability measures: Temporal domain 4/26/05 Kantipudi: ELEC 7250 2

Why we need them? n We need testability information of a circuit Why? Ø Ø DFT (Design-For-Testability) We need module-level or Register-Transfer-level measures for this Why? There will be no independent gates in VLSI circuits ATPG (Automatic Test Pattern Generation) We need gate-level measures for this Why? We need to know the easily controllable and observable nodes in a ckt Why? 4/26/05 Kantipudi: ELEC 7250 3

Gate-level Testability Measures: SCOAP L. H. Goldstein, "Controllability / Observability Analysis of Digital Circuits" n n n combinational zero controllability (CC 0) combinational one controllability (CC 1) combinational observability (CO) sequential zero controllability (SC 0) sequential one controllability (SC 1) sequential observability (SO) Primary Inputs: The combinational controllabilities(CC 0 & CC 1) are set to ‘ 1’ and all sequential controllabilities(SC 0 & SC 1) are set to ‘ 0’ Primary Outputs: Both combinational and sequential observabilities are set to ‘ 0’ 4/26/05 Kantipudi: ELEC 7250 4

NAND Gate: But every ATMG has a restriction: It has to be linear. It cannot be NP-Complete SCOAP: All inputs to all logic elements are independent What about reconvergent fan-outs? A CC 1(I) CC 0(Z) 4/26/05 CC 0(Z) CC 1(I) Kantipudi: ELEC 7250 B CC 0(Z) = CC 1(I) + 1 CC 0(Z) = CC 1(A) + CC 1(B) + 1 = 2 CC 1(I) + 1 5

High level Testability Measures q Module-level measures: ü ü ü q Every module has its own characteristic Function A probability spectrum from the truth-tables of prim. o/ps of modules C & O values are calculated from the probability spectrum Register-Transfer-level measures: (J. E. Stephenson and J. Grason ’ 76) ü As network of components interconnected by unidirectional links ü Two tasks: ü Control Task: Propagating controllability from the circuit primary inputs, through other components, to the inputs of the component ü Observation Task: Propagating observability from the outputs of the component through other components to the primary outputs of the circuit ü Controllability(CY) and Observability(OY) of each node is calculated using complex formulae. 4/26/05 Kantipudi: ELEC 7250 6 TMEAS

Detection probability using testability measures: V. D. Agrawal and M. R. Mercer, “Testability Measures-What Do They Tell Us? ” Represented detection probability as an exponential function: So, the fault coverage is given by: Gives only a rough estimation of fault coverage. Found that 70% of the hard-to-test faults are actually detectable. Inference: “Testability measures cannot be the only criteria for DFT. ” 4/26/05 Kantipudi: ELEC 7250 7

Future needs: n n Need for accurate testability measures Need more ATMG tools like TMEAS and ITTAP Conclusion: v. The present accuracy of testability measures is not enough; For them to be the only criteria in DFT v. Dynamic testability measures will be of much more help for an ATPG. 4/26/05 Kantipudi: ELEC 7250 8