Concluding Remarks SOAP 3152002 CSE 141 Final Remarks

  • Slides: 18
Download presentation
Concluding Remarks SOAP 3/15/2002 CSE 141 - Final Remarks

Concluding Remarks SOAP 3/15/2002 CSE 141 - Final Remarks

Computer Technologies • First Generation: Mid 40’s to late 50’s – Vacuum Tube “switches”

Computer Technologies • First Generation: Mid 40’s to late 50’s – Vacuum Tube “switches” – Acoustic or CRT memory (volatile) • Second Generation: Late 50’s to mid 60’s – Individual transistors – Core memory, magnetic disks (non-volatile) • Third Generation: Mid 60’s to mid 70’s – Integrated circuits (up to 1000 transistors/chip) – Complex instructions via microcode • Fourth Generation: Mid 70’s and beyond – single-chip processors; semiconductor memory 2 CSE 141 - Final Remarks

Computer Taxonomy • Supercomputer • Parallel or vector machine, fast memory, cost > $1

Computer Taxonomy • Supercomputer • Parallel or vector machine, fast memory, cost > $1 M • Mainframe, Server • Typically serve 100’s of users; lots of I/O power • Workstation • High performance; less I/O than mainframe • 1 -10 users, often UNIX operating system • Personal Computer The difference between these two is disappearing • Single user, < $3000, often Microsoft or MAC OS. • Embedded computer or controller 3 • Special-purpose interface: gameboys, microwaves, . . . CSE 141 - Final Remarks

The computer pyramid There are far more lower-layer computers than higher, more powerful ones.

The computer pyramid There are far more lower-layer computers than higher, more powerful ones. Innovations move from top to bottom (usually). But supercomputers are being replaced by interconnected workstations & PC’s (and Playstations? ? ). Super – computers Servers Workstations Personal Computers Embedded Controllers 4 CSE 141 - Final Remarks

What is this course all architecture about? 1. Layers of Abstraction 1. ISA’s, bus

What is this course all architecture about? 1. Layers of Abstraction 1. ISA’s, bus standards (e. g. PCI, Ethernet, . . . ), Virtual Memory 2. Good (or popular) standards evolve and outlive individual machines • E. g. IBM 360, Intel x 86 2. Interfacing We’ve had to consider programming languages, compilers, operating systems, networks, . . . 3. Performance. . . 5 CSE 141 - Final Remarks

Memory Evolution • Transistors get smaller, resulting in. . . A slide from beginning

Memory Evolution • Transistors get smaller, resulting in. . . A slide from beginning of course • DRAM chip capacity doubles every 1. 5 years Processor Evolution • Transistor count doubles every 2 years • Clock speed doubles every 3 years • Memory speeds increase a tiny bit And then a miracle occurs. . . • Performance doubles every 1. 5 years 6 CSE 141 - Final Remarks

Processor Architecture Program Counter Instruction Register Control 7 Load Store Registers ALU CSE 141

Processor Architecture Program Counter Instruction Register Control 7 Load Store Registers ALU CSE 141 - Final Remarks

pipeline the ALU Program Counter Instruction Register Control 8 Load Store Registers Pipelined ALU

pipeline the ALU Program Counter Instruction Register Control 8 Load Store Registers Pipelined ALU CSE 141 - Final Remarks

separate fixed & float Program Counter Load Store Instruction Register Integer Registers Control 9

separate fixed & float Program Counter Load Store Instruction Register Integer Registers Control 9 Intege r pipe Float Registers Floating Point pipe CSE 141 - Final Remarks

add branch prediction Program Counter Load Store Instruction Register Integer Registers Control + Branch

add branch prediction Program Counter Load Store Instruction Register Integer Registers Control + Branch Prediction 10 Intege r pipe Float Registers Floating Point pipe CSE 141 - Final Remarks

out-of-order execution Program Counter Instruction Register File Control, Branch Prediction, Out. Of. Order 11

out-of-order execution Program Counter Instruction Register File Control, Branch Prediction, Out. Of. Order 11 Load Store Integer Registers + shadow registers Intege r pipe Float Registers + shadow registers Floating Point pipe CSE 141 - Final Remarks

more functional units Program Counter Instruction Register File Control, Branch Prediction, Out. Of. Order

more functional units Program Counter Instruction Register File Control, Branch Prediction, Out. Of. Order 12 Load Store Integer Registers + shadow registers Intege r Intege pipe r pipe Load Store Float Registers + shadow registers Floating Point Floating pipe Point pipe CSE 141 - Final Remarks

on-chip memory caches Program Counter Instruction Register File Load Store TLB Load Store Integer

on-chip memory caches Program Counter Instruction Register File Load Store TLB Load Store Integer Registers + shadow registers Level 2 Cache Instruction Cache Control, Branch Prediction, Out. Of. Order 13 Load Store Float Registers + shadow registers Data Cache Intege r Intege pipe r pipe Floating Point Floating pipe Point pipe CSE 141 - Final Remarks

Speculation What has changed? Amount of on-chip concurrency What hasn’t changed (yet)? The program

Speculation What has changed? Amount of on-chip concurrency What hasn’t changed (yet)? The program counter Coming to your computer soon. . . Multithreaded Architectures Small changes to microprocessor: - add 3 - 7 program counters and register sets 14 CSE 141 - Final Remarks

The Final • Tuesday, March 19, 11: 30 – 2: 29 – Last names

The Final • Tuesday, March 19, 11: 30 – 2: 29 – Last names A – M : Center 113 (classroom) – Last names N – Z : CSB 001 (section room) • You may bring: – 3 pages of handwritten notes – Calculators (though I still don’t understand how they help!) – A little odorless food 15 CSE 141 - Final Remarks

What’s on the Final ? ? • Entire course – Including things that weren’t

What’s on the Final ? ? • Entire course – Including things that weren’t on quizzes: • E. g. branch hazards, superscalar scheduling • Similar to quizzes: – Some easier questions, some harder – Vocabulary, details (control lines, cache operation, . . . ), reasons for various choices, calculations. – Including a Bot. EE (Back of the Envelope Estimate) Note: For other problems, don’t round off answers 16 CSE 141 - Final Remarks

Quiz 3, last question • Data moves from Ethernet Controller to Memory on System

Quiz 3, last question • Data moves from Ethernet Controller to Memory on System Bus. – Only one pair of devices can use a bus at a time. – So, processor-memory communication is disrupted. • Total amount of data moved on System Bus per image 1 MByte: Ethernet Controller to Memory 1 MByte: Memory into Cache first time (compulsory misses) 2 MByte: Extra trips of data into cache (it keeps getting kicked out) 4 MByte total Total system speed is limited by: With Fast Ethernet, getting data from cameras to Ethernet Controller With Gigabit Ethernet, the System Bus limits performance Processor and Caches System bus Ethernet #1 remote sensors 17 Ethernet Controller Memory Ethernet #2 remote sensors CSE 141 - Final Remarks

Grading Quiz 1 Hi 27. 5 (out of 30) Top quartile: 21. 5 Median:

Grading Quiz 1 Hi 27. 5 (out of 30) Top quartile: 21. 5 Median: 18 Third Quartile: 15 Quiz 2 Add 10 to Quiz 1 score High 38 (out of 40) Top quartile: 34 Median: 31. 5 Third quartile: 27. 5 Quiz 3 Hi 28 (out of 29) Top quartile: 20 Median: 17. 5 Third quartile: 15 18 Add 11 to Quiz 1 score 30 is “B” (and closer to B+ than B-) CSE 141 - Final Remarks