ComputerAided Design of ASICs Concept to Silicon Victor

Computer-Aided Design of ASICs Concept to Silicon Victor P. Nelson

ASIC Design Flow Behavioral Model Verify Function VHDL/Verilog Front-End Design Synthesis DFT/BIST & ATPG Gate-Level Netlist Full-custom IC Test vectors Standard Cell IC & FPGA/CPLD DRC & LVS Verification Verify Function Transistor-Level Netlist Physical Layout Map/Place/Route Verify Function & Timing Back-End Design Verify Timing IC Mask Data/FPGA Configuration File

ASIC CAD tools available in ECE � Modeling and Simulation � Modelsim, ADVance MS/Questa, Eldo, Mach TA/ADi. T (Mentor Graphics) � Verilog-XL, NC_Verilog, Spectre (Cadence) � Design Synthesis (digital) � Leonardo Spectrum, Precision RTL (Mentor Graphics) � Design Compiler (Synopsys), RTL Compiler (Cadence) � Design for Test and Automatic Test Pattern Generation � DFT Advisor, Fastscan, Flextest (Mentor Graphics) � Schematic Capture & Design Integration � Design Architect-IC (Mentor Graphics) � Design Framework II (DFII) - Composer (Cadence) � Physical Layout � IC Station (Mentor Graphics) � SOC Encounter, Virtuoso (Cadence) � Design Verification � Calibre (Mentor Graphics) � Diva, Assura (Cadence)

Mentor Graphics Analog/Mixed. Signal IC Design Flow

Mentor Graphics CAD Tools (select from “eda” list in user-setup on the Sun network) � ICFlow** – For custom & standard cell IC designs � IC flow tools (Design Architect-IC, IC Station, Calibre) � Digital/analog/mixed simulation (Modelsim, ADVance MS, Eldo, Mach. TA) � HDL Synthesis (Leonardo) � ASIC Design Kit (ADK)** Support files for various technologies � DFT � ATPG/DFT/BIST tools (DFT Advisor, Flextest, Fastscan) � Modelsim** (HDL Simulation) � FPGA (FPGA Advantage, Modelsim, Leonardo) � *Xilinx/ISE (Xilinx FPGA/CPLD - back end design) � *Quartus. II (Altera FPGA/CPLD - back end design) � *Ims/6. 2 (IMS chip tester) ** Installed on both Solaris and Linux servers * Vendor-Provided (Not Mentor Graphics) Tools

Mentor Graphics ASIC Design Kit (ADK) � Technology files & standard cell libraries �AMI: ami 12, ami 05 (1. 2, 0. 5 μm) �TSMC: tsmc 035, tsmc 025, tsmc 018 (0. 35, 0. 25, 0. 18 μm) � IC flow & DFT tool support files: �Simulation � VHDL/Verilog/Mixed-Signal models (Modelsim SE/ADVance MS) � Analog (SPICE) models (Eldo/Accusim) � Post-layout timing (Mach TA) � Digital schematic (Quicksim II, Quicksim Pro) (except tsmc 025, tsmc 018) �Synthesis to standard cells (Leonardo. Spectrum) �Design for test & ATPG (DFT Advisor, Flextest/Fastscan) �Schematic capture (Design Architect-IC) �IC physical design (standard cell & custom) � Floorplan, place & route (IC Station) � Design rule check, layout vs schematic, parameter extraction (Calibre) We also have ADK’s for Cadence tools for several technologies

Xilinx/Altera FPGA/CPLD Design Tools � Simulate designs in Modelsim �Behavioral models (VHDL, Verilog) �Synthesized netlists (VHDL, Verilog) � Requires “primitives” library for the target technology � Synthesize netlist from behavioral model �Leonardo (Levels 1, 2, 3) has libraries for most FPGAs (ASIC-only version currently installed) �Xilinx ISE has its own synthesis tool � Vendor tools for back-end design �Map, place, route, configure device, timing analysis, generate timing models �Xilinx Integrated Software Environment (ISE) �Altera Quartus II & Max+Plus 2 � Higher level tools for system design & management �Mentor Graphics FPGA Advantage �Xilinx Platform Studio : So. C design, IP management, HW/SW codesign

Behavioral Design & Verification VHDL Verilog System. C Modelsim (digital) VHDL-AMS Verilog-A Create Behavioral/RTL HDL Model(s) Simulate to Verify Functionality Synopsys Design Compiler Leonardo Spectrum, Xilinx ISE (digital) ADVance MS (analog/mixed signal) Synthesize Circuit Design Constraints Simulate to Verify Function/Timing Technology-Specific Netlist to Back-End Tools Technology Libraries VITAL Library

ADVance MS Digital, Analog, Mixed-Signal Simulation VHDL, Verilog, VHDL-AMS, Verilog-A, SPICE Netlists Working Library Simulation Setup Eldo, Eldo RF Analog Mach TA (SPICE) Mach PA Design_1 Design_2 VITAL SPICE Xilinx models SIMPRIMS IEEE 1164 Resource Libraries ADVance MS EZwave or Xelga View Results Input Stimuli Modelsim Digital (VHDL, Verilog) Mixed Signal (VHDL-AMS, Verilog-A)

ADVance MS : mixed-signal simulation A/D converter digital analog VHDL-AMS

ADVance MS: mixed Verilog-SPICE Verilog top (test bench) SPICE subcircuit

Questa ADMS (replaces ADVance MS) �Four simulation engines integrated for So. C designs �Questa – VHDL/Verilog/System. C digital simulation �Eldo – analog (SPICE) simulation �ADi. T – accelerated transistor-level (Fast-SPICE) simulation (replaces Mach TA) �Eldo RF �Engines and languages can be mixed in a simulation �IEEE 1497 Standard Delay File Format (SDF) �IEEE 1076. 1 VHDL-AMS �IEEE 1076 VHDL �IEEE 1364 Verilog �IEEE 1800 System. Verilog �IEEE 1666 System. C �Accellera standard Verilog-AMS Language �SPICE Eldo, HSPICE, and Spectre dialects.

Questa ADMS

Example: 4 -bit binary counter �VHDL model (count 4. vhd) �Create working library: vlib work vmap work �Compile: vcom count 4. vhd �Simulate: vsim count 4(rtl) �Model. Sim simulation-control inputs �Model. Sim “Macro” (count 4_rtl. do) �OR, VHDL testbench �Model. Sim results �listing or waveform

-- count 4. vhd 4 -bit parallel-load synchronous counter LIBRARY ieee; USE ieee. std_logic_1164. all; USE ieee. numeric_std. all; --synthesis libraries ENTITY count 4 IS PORT (clock, clear, enable, load_count : IN STD_LOGIC; D: IN unsigned(3 downto 0); Q: OUT unsigned(3 downto 0)); END count 4; ARCHITECTURE rtl OF count 4 IS SIGNAL int : unsigned(3 downto 0); BEGIN PROCESS(clear, clock, enable) BEGIN IF (clear = '1') THEN int <= "0000"; ELSIF (clock'EVENT AND clock='1') THEN IF (enable = '1') THEN IF (load_count = '1') THEN int <= D; ELSE int <= int + "01"; END IF; END PROCESS; Q <= int; END rtl;

Test stimulus: Modelsim “do” file: count 4_rtl. do add wave /clock /clear /enable /load_count /D /Q add list /clock /clear /enable /load_count /D /Q force /clock 0 0, 1 10 -repeat 20 force /clear 0 0, 1 5, 0 10 force /enable 0 0, 1 25 force /load_count 0 0, 1 20, 0 35, 1 330, 0 350 force /D 10#5 0, 10#9 300 run 400

Testbench: count 4_bench. vhd LIBRARY ieee; USE ieee. std_logic_1164. all; USE ieee. numeric_std. all; ENTITY count 4_bench is end count 4_bench; ARCHITECTURE test of count 4_bench is component count 4 PORT (clock, clear, enable, load_count : IN STD_LOGIC; D: IN unsigned(3 downto 0); Q: OUT unsigned(3 downto 0)); end component; for all: count 4 use entity work. count 4(behavior); signal clk : STD_LOGIC : = '0'; signal clr, en, ld: STD_LOGIC; signal din, qout: unsigned(3 downto 0); begin UUT: count 4 port map(clk, clr, en, ld, din, qout); clk <= not clk after 10 ns; P 1: process begin din <= "0101"; clr <= '1'; en <= '1'; ld <= '1'; wait for 10 ns; clr <= '0'; wait for 20 ns; ld <= '0'; wait for 200 ns; end process; end; Alternative to “do” file Could also check results & “assert” error messages

Count 4 – Simulation waveform Clear Counting Parallel Load

Automated Synthesis with Leonardo Spectrum Technology Synthesis Libraries FPGA VHDL/Verilog Behavioral/RTL Models Leonardo Spectrum (Level 3) Design Constraints ASIC ADK AMI 0. 5, 1. 2 TSMC 0. 35, 0. 25 Technology. Specific Netlist VHDL, Verilog, SDF, EDIF, XNF Level 1 – FPGA Level 2 – FPGA + Timing Level 3 – ASIC + FPGA (we have Level 3 ASIC only)

Automated Synthesis with Synopsys Design Compiler Technology Synthesis Libraries ASIC VHDL/Verilog Behavioral/RTL Models Design Compiler (shell) Design Vision (GUI) DW Synopsys Design. Ware Component Library Technology. Specific Netlist Verilog, SDF, DDC database, SDC constraints, REP report Design Constraints

Leonardo – ASIC Synthesis Flow Synthesize generic gates & modules Read & check HDL Map to technology cells & optimize Write netlist, SDF, reports

Leonardo synthesis procedure 1. 2. Invoke leonardo Select & load a technology library (ASIC or FPGA) � 3. 4. 5. 6. ASIC > ADK > TSMC 0. 35 micron Read input VHDL/Verilog file(s): count 4. vhd Enter design constraints (clock freq, delays, etc. ) Optimize for area/delays/effort level Write output file(s) � � count 4_0. vhd count 4. v count 4. sdf count 4. edf - VHDL netlist - Verilog netlist (for IC layout) - Standard delay format file (for timing) - EDIF netlist (for Xilinx/Altera FPGA)

Leonardo-synthesized netlist count 4_0. vhd library IEEE; use IEEE. STD_LOGIC_1164. all; library adk; use adk_components. all; -- ADDED BY VPN entity count 4 is port ( clock : IN std_logic ; clear : IN std_logic ; enable : IN std_logic ; load_count : IN std_logic ; D : IN std_logic_vector (3 DOWNTO 0) ; Q : OUT std_logic_vector (3 DOWNTO 0)) ; end count 4 ; architecture netlist of count 4 is -- rtl changed to netlist by VPN signal Q_3_EXMPLR, Q_2_EXMPLR, Q_1_EXMPLR, Q_0_EXMPLR, nx 8, nx 14, nx 22, nx 28, nx 48, nx 54, nx 62, nx 126, nx 136, nx 146, nx 156, nx 169, nx 181, nx 183, nx 185, nx 187, nx 189: std_logic ; begin Q(3) <= Q_3_EXMPLR ; Q(2) <= Q_2_EXMPLR ; Q(1) <= Q_1_EXMPLR ; Q(0) <= Q_0_EXMPLR ; Q_0_EXMPLR : dffr port map ( Q=>Q_0_EXMPLR, QB=>OPEN, D=>nx 126, CLK=>clock, R=>clear); ix 127 : mux 21_ni port map ( Y=>nx 126, A 0=>Q_0_EXMPLR, A 1=>nx 8, S 0=>enable ); ix 9 : oai 21 port map ( Y=>nx 8, A 0=>load_count, A 1=>Q_0_EXMPLR, B 0=>nx 169 ); ix 170 : nand 02 port map ( Y=>nx 169, A 0=>D(0), A 1=>load_count); Q_1_EXMPLR : dffr port map ( Q=>Q_1_EXMPLR, QB=>OPEN, D=>nx 136, CLK=>clock, R=>clear); ix 137 : mux 21_ni port map ( Y=>nx 136, A 0=>Q_1_EXMPLR, A 1=>nx 28, S 0=> enable); ix 29 : ao 22 port map ( Y=>nx 28, A 0=>D(1), A 1=>load_count, B 0=>nx 14, B 1=> nx 22); ix 15 : or 02 port map ( Y=>nx 14, A 0=>Q_0_EXMPLR, A 1=>Q_1_EXMPLR); ix 23 : aoi 21 port map ( Y=>nx 22, A 0=>Q_1_EXMPLR, A 1=>Q_0_EXMPLR, B 0=> load_count); Q_2_EXMPLR : dffr port map ( Q=>Q_2_EXMPLR, QB=>OPEN, D=>nx 146, CLK=>clock, R=>clear); ix 147 : mux 21_ni port map ( Y=>nx 146, A 0=>Q_2_EXMPLR, A 1=>nx 48, S 0=> enable); ix 49 : oai 21 port map ( Y=>nx 48, A 0=>nx 181, A 1=>nx 183, B 0=>nx 189); ix 182 : aoi 21 port map ( Y=>nx 181, A 0=>Q_1_EXMPLR, A 1=>Q_0_EXMPLR, B 0=> Q_2_EXMPLR); ix 184 : nand 02 port map ( Y=>nx 183, A 0=>nx 185, A 1=>nx 187); ix 186 : inv 01 port map ( Y=>nx 185, A=>load_count); ix 188 : nand 03 port map ( Y=>nx 187, A 0=>Q_2_EXMPLR, A 1=>Q_1_EXMPLR, A 2=> Q_0_EXMPLR); ix 190 : nand 02 port map ( Y=>nx 189, A 0=>D(2), A 1=>load_count); Q_3_EXMPLR : dffr port map ( Q=>Q_3_EXMPLR, QB=>OPEN, D=>nx 156, CLK=>clock, R=>clear); ix 157 : mux 21_ni port map ( Y=>nx 156, A 0=>Q_3_EXMPLR, A 1=>nx 62, S 0=> enable); ix 63 : mux 21_ni port map ( Y=>nx 62, A 0=>nx 54, A 1=>D(3), S 0=>load_count); ix 55 : xnor 2 port map ( Y=>nx 54, A 0=>Q_3_EXMPLR, A 1=>nx 187); end netlist ;

// Verilog description for cell count 4, Leonardo. Spectrum Level 3, 2005 a. 82 module count 4 ( clock, clear, enable, load_count, D, Q ) ; input clock ; input clear ; input enable ; input load_count ; input [3: 0]D ; output [3: 0]Q ; wire nx 8, nx 14, nx 22, nx 28, nx 48, nx 54, nx 62, nx 126, nx 136, nx 146, nx 156, nx 169, nx 181, nx 183, nx 185, nx 187, nx 189; wire [3: 0] $dummy ; dffr Q_0__rename (. Q (Q[0]), . QB ($dummy [0]), . D (nx 126), . CLK (clock), . R (clear)) ; mux 21_ni ix 127 (. Y (nx 126), . A 0 (Q[0]), . A 1 (nx 8), . S 0 (enable)) ; oai 21 ix 9 (. Y (nx 8), . A 0 (load_count), . A 1 (Q[0]), . B 0 (nx 169)) ; nand 02 ix 170 (. Y (nx 169), . A 0 (D[0]), . A 1 (load_count)) ; dffr Q_1__rename (. Q (Q[1]), . QB ($dummy [1]), . D (nx 136), . CLK (clock), . R (clear)) ; mux 21_ni ix 137 (. Y (nx 136), . A 0 (Q[1]), . A 1 (nx 28), . S 0 (enable)) ; ao 22 ix 29 (. Y (nx 28), . A 0 (D[1]), . A 1 (load_count), . B 0 (nx 14), . B 1 (nx 22) ) ; or 02 ix 15 (. Y (nx 14), . A 0 (Q[0]), . A 1 (Q[1])) ; aoi 21 ix 23 (. Y (nx 22), . A 0 (Q[1]), . A 1 (Q[0]), . B 0 (load_count)) ; dffr Q_2__rename (. Q (Q[2]), . QB ($dummy [2]), . D (nx 146), . CLK (clock), . R (clear)) ; mux 21_ni ix 147 (. Y (nx 146), . A 0 (Q[2]), . A 1 (nx 48), . S 0 (enable)) ; oai 21 ix 49 (. Y (nx 48), . A 0 (nx 181), . A 1 (nx 183), . B 0 (nx 189)) ; aoi 21 ix 182 (. Y (nx 181), . A 0 (Q[1]), . A 1 (Q[0]), . B 0 (Q[2])) ; nand 02 ix 184 (. Y (nx 183), . A 0 (nx 185), . A 1 (nx 187)) ; inv 01 ix 186 (. Y (nx 185), . A (load_count)) ; nand 03 ix 188 (. Y (nx 187), . A 0 (Q[2]), . A 1 (Q[1]), . A 2 (Q[0])) ; nand 02 ix 190 (. Y (nx 189), . A 0 (D[2]), . A 1 (load_count)) ; dffr Q_3__rename (. Q (Q[3]), . QB ($dummy [3]), . D (nx 156), . CLK (clock), . R (clear)) ; mux 21_ni ix 157 (. Y (nx 156), . A 0 (Q[3]), . A 1 (nx 62), . S 0 (enable)) ; mux 21_ni ix 63 (. Y (nx 62), . A 0 (nx 54), . A 1 (D[3]), . S 0 (load_count)) ; xnor 2 ix 55 (. Y (nx 54), . A 0 (Q[3]), . A 1 (nx 187)) ; endmodule

Post-synthesis simulation (Leonardo-generated netlist) �Verify synthesized netlist matches behavioral models �Create library of std cell simulation. VITAL primitives: of ADK std cells >vlib adk >vcom $ADK/technology/adk. vhd >vcom $ADK/technology/adk_comp. vhd �Insert library/package declaration into netlist library adk; use adk_components. all; � Simulate in Modelsim, using “do file” or test bench from original behavioral simulation �results should match

Post-synthesis timing analysis � Leonardo can generate SDF (std. delay format) file with technology-specific, VITAL-compliant timing parameters (from cell library) (CELLTYPE "dffr") (INSTANCE Q_0_EXMPLR) (DELAY (ABSOLUTE (PORT D (: : 0. 00)) (PORT CLK (: : 0. 00)) (PORT R (: : 0. 00)) (IOPATH CLK Q (: : 0. 40) (: : 0. 47)) (IOPATH R Q (: : 0. 00) (: : 0. 55)) (IOPATH CLK QB (: : 0. 45) (: : 0. 36)) (IOPATH R QB (: : 0. 53) (: : 0. 00)))) (TIMINGCHECK (SETUP D (posedge CLK) (0. 47)) (HOLD D (posedge CLK) (-0. 06)))) Delays lumped at pins Path delays (min: typ: max) Constraints

VITAL Model (1) library IEEE; use IEEE. STD_LOGIC_1164. all; use IEEE. VITAL_Primitives. all; use IEEE. VITAL_Timing. all; entity and 02 is generic ( tipd_A 0 : Vital. Delay. Type 01 Z : = Vital. Zero. Delay 01 Z; tipd_A 1 : Vital. Delay. Type 01 Z : = Vital. Zero. Delay 01 Z; Delays from SDF file tpd_A 0_Y : Vital. Delay. Type 01 Z : = Vital. Zero. Delay 01 Z; tpd_A 1_Y : Vital. Delay. Type 01 Z : = Vital. Zero. Delay 01 Z ); port ( A 0 : in STD_LOGIC; A 1 : in STD_LOGIC; Y : out STD_LOGIC ); attribute VITAL_LEVEL 0 of and 02 : entity is TRUE; end and 02;

VITAL Model (2) architecture and 02_arch of and 02 is attribute VITAL_LEVEL 1 of and 02_arch : architecture is TRUE; signal A 0_ipd : STD_LOGIC : = 'X'; signal A 1_ipd : STD_LOGIC : = 'X'; begin Wire. Delay : Block begin Determine input Vital. Wire. Delay (A 0_ipd, A 0, tipd_A 0); pin delays Vital. Wire. Delay (A 1_ipd, A 1, tipd_A 1); end Block; Vital. Behavior : Process (A 0_ipd, A 1_ipd) VARIABLE INT_RES_0 : STD_LOGIC : = 'X'; VARIABLE Glitch. Data_Y : Vital. Glitch. Data. Type; begin -- FUNCTIONALITY SECTION -Ideal (zero-delay) INT_RES_0 : = Vital. And 2 (A 0_ipd, A 1_ipd); AND function

VITAL Model (3) -PATH DELAY SECTION -Vital. Path. Delay 01 Z ( Out. Signal => Y, Determine delay along Out. Signal. Name => "Y", each input-output path Out. Temp => INT_RES_0, Paths => ( 0 => ( Input. Change. Time => A 0_ipd'LAST_EVENT, Path. Delay => tpd_A 0_Y, Path. Condition => TRUE ), 1 => ( Input. Change. Time => A 1_ipd'LAST_EVENT, Path. Delay => tpd_A 1_Y, Path. Condition => TRUE ) ), Glitch. Data => Glitch. Data_Y, Mode => On. Detect, Msg. On => TRUE, Xon => TRUE, Msg. Severity => WARNING

Design for test & test generation �Consider test during the design phase �Test design more difficult after design frozen �Basic steps: �Design for test (DFT) – insert test points, scan chains, etc. to improve testability �Insert built-in self-test (BIST) circuits �Generate test patterns (ATPG) �Determine fault coverage (Fault Simulation)

DFT & test design flow Memory & Logic BIST Boundary Scan Internal Scan Design ATPG

DFTadvisor/Fast. Scan Design Flow count 4. vhd Leonardo DFT/ATPG Library: count 4_0. vhd count 4. v count 4_scan. v adk. atpg Source: Flex. Test Manual

ASIC DFT Flow Synthesized VHDL/Verilog Netlist ATPG Library DFT Advisor Insert Internal Scan Circuitry VHDL/Verilog Netlist With Scan Elements Fastscan/ Flextest Generate/Verify Test Vectors Test Pattern File adk. atpg

Example DFTadvisor session � Invoke: �dftadvisor –verilog count 4. v –lib $ADK/technology/adk. atpg � Implement scan with defaults: (full scan, mux-DFF scan elements) �set system mode setup �analyze control signals –auto �set system mode dft �run �insert test logic �write netlist count 4_scan. v –verilog �write atpg setup count 4_scan (creates count 4_scan. dofile for ATPG in Fastscan)

count 4 – without scan design

count 4 – scan inserted by DFTadvisor

ATPG with Fast. Scan (full-scan circuit) �Invoke: �fastscan –verilog count 4. v –lib $ADK/technology/adk. atpg �Generate test pattern file in Fast. Scan: �dofile count 4_scan. dofile (defines scan path & procedure) ** �set system mode atpg �create patterns –auto (generate test patterns) �save patterns ** “count 4_scan. dofile” was created by DFTadvisor

Test file: scan chain definition and load/unload procedures scan_group "grp 1" = scan_chain "chain 1" = scan_in = "/scan_in 1"; scan_out = "/output[3]"; length = 4; end; procedure shift "grp 1_load_shift" = force_sci "chain 1" 0; force "/clock" 1 20; force "/clock" 0 30; period 40; end; procedure shift "grp 1_unload_shift" = measure_sco "chain 1" 10; force "/clock" 1 20; force "/clock" 0 30; period 40; end; procedure load "grp 1_load" = force "/clear" 0 0; force "/clock" 0 0; force "/scan_en" 1 0; apply "grp 1_load_shift" 4 40; end; procedure unload "grp 1_unload" = force "/clear" 0 0; force "/clock" 0 0; force "/scan_en" 1 0; apply "grp 1_unload_shift" 4 40; end;

Generated scan-based test // send a pattern through the scan chain CHAIN_TEST = pattern = 0; apply "grp 1_load" 0 = (use grp 1_load procedure) chain "chain 1" = "0011"; (pattern to scan in) end; apply "grp 1_unload" 1 = (use grp 1_unload procedure) chain "chain 1" = "1100"; (pattern scanned out) end; // one of 14 patterns for the counter circuit pattern = 0; (pattern #) apply "grp 1_load" 0 = (load scan chain) chain "chain 1" = "1000"; (scan-in pattern) end; force "PI" "00110" 1; (PI pattern) measure "PO" "0010" 2; (expected POs) pulse "/clock" 3; (normal op. cycle) apply "grp 1_unload" 4 = (read scan chain) chain "chain 1" = "0110"; (expected pattern) end;

ASIC Physical Design (Standard Cell) (can also do full custom layout) Component-Level Netlist (EDDM format) Std. Cell Layouts Floorplan Chip/Block Libraries Mentor Graphics “IC Station” (adk_ic) ICblocks Process Data Place & Route Std. Cells Design Rules Generate Mask Data Design Rule Check Calibre IC Mask Data Backannotate Schematic Calibre Layout vs. Schematic Check Calibre Mach TA/Eldo Simulation Model

Cell-Based IC I/O pads

Cell-Based Block

Basic standard Cell layout Source: Weste “CMOS VLSI Design”

Preparation for Layout 1. Use Design Architect-IC to convert Verilog netlist to Mentor Graphics EDDM netlist format � � Invoke Design Architect-IC (adk_daic) On menu bar, select File > Import Verilog � � � 2. Open the generated schematic for viewing � � � 3. Netlist file: count 4. v (the Verilog netlist) Output directory: count 4 (for the EDDM netlist) Mapping file $ADK/technology/adk_map. vmp Click Schematic in DA-IC palette Select schematic in directory named above (see next slide) Click Update LVS in the schematic palette to create a netlist to be used later by “Calibre” Create design viewpoints for ICstation tools � adk_dve count 4 –t tsmc 035 (V. P’s: layout, lvs, sdl, tsmc 035) Can also create gate/transistor schematics directly in DA -IC using components from the ADK library

DA-IC generated schematic

Eldo simulation from DA-IC �Run simulations from within DA-IC �Eldo, ADVance MS, Mach TA �DA-IC invokes a “netlister” to create a circuit model from the schematic �SPICE model for Eldo & Mach TA �Eldo analyses, forces, probes, etc. same as SPICE �View results in EZwave

Eldo input and output files -Netlist -Simulation cmds -Stimulus

SPICE “circuit” file generated by DA-IC From ADK library Force values (created interactively) SPICE netlist for modulo 7 counter

Force functions (1) �DC value �Vsigname A 0 DC 5 V indicates voltage Force name Between circuit nodes A and GND (node 0) Value (volts)

Force functions (2) �Pulse/square wave �Vsigname B 0 pulse 0 5 0 0. 1 N 20 N 40 N Nodes Initial Pulsed Voltage v 1 v 2 tp v 2 v 1 td tr tw tf Rise Fall time tr tf Pulse Period width tp tw Delay from start of period for waveform to begin - td

Force functions (3) (for logic 0 & 1 values) Vname B 0 pattern 5 0 5 n 0. 1 n 10 n 011010 R �Pattern wave Bit pattern Rise & Fall Time between Logic 1 & 0 voltages Delay tochanges Duration of bit value waveform Between circuit Nodes B & GND (node 0) begin 1 0 delay 1 1 0 pattern 0 Repeat the pattern (optional)

Eldo simulation of modulo 7 counter (transient analysis)

Create a std-cell based logic block in IC Station �Invoke: adk_ic �In IC Station palette, select: Create Cell �Cell name: count 4 �Attach cell library: $ADK/technology/ic/process/tsmc 035 �Process data: $ADK/technology/ic/process/tsmc 035 �Design rules: $ADK/technology/ic/process/tsmc 035. rules �Angle mode: 45 �Cell type: block �Select With connectivity (use imported schematic) �EDDM schematic viewpoint: count 4/layout �Logic loading options: flat

Create Cell dialog box

Auto-”floorplan” the block place & route > autofp

Auto-place the std cells Autoplc > Std. Cel

Auto-place ports (signal connections on cell boundaries) Autoplc > Ports

Auto. Route all nets (hand-route any unrouted “overflows”) Then: Add > Port Text to copy port names from schematic – for Calibre

Layout design rule check (DRC) �Technology-specific design rules specify minimum sizes, spacing, etc. of features to ensure reliable fabrication �Design rules file specified at startup Ex. tsmc 035. rules �From main palette, select ICrules �Click Check and then OK in prompt box (can optionally select a specific area to check) �Rules checked in numeric order

Common errors detected by DRC �To fix, click on First in palette to highlight first error �Error is highlighted in the layout �Click View to zoom in to the error (see next) �Example: DRC 9_2: Metal 2 spacing = 3 L �Fix by drawing a rectangle of metal 2 to fill in the gap between contacts that should be connected �Click Next to go to next error, until all are fixed NOTE: There can be no DRC errors if MOSIS is to fabricate the chip – they will run their own DRC.

Sample error: DRC 9_2 metal 2 spacing = 3 L Draw rectangle of metal 2 to fill gap It also called contact-to-contact metal 2 spacing DRC 9_2 error

Layout vs schematic check using Calibre Interactive LVS �Compare extracted transistor-level netlist against netlist saved in DA-IC �From ICstation menu: Calibre > Run LVS �In popup, Calibre location: $MGC_HOME/. . /Calibre �Rules: $ADK/technology/ic/process/tsmc 035. calibre. rules �Input: count 4. src. net (previously created in DA-IC) �H-cells: $ADK/technology/adk. hcell (hierarchical cells) �Extracted file: count 4. lay. net

Post-layout parameter extraction via Calibre Interactive PEX �Extract Spice netlist, including parasitic RC �Simulate in Eldo or Mach. TA �ICstation menu: Calibre>Run PEX �Options similar to Calibre LVS �Extraction options: �lumped C + coupling cap’s �distributed RC + coupling cap’s �Output file: count 4. pex. netlist

Post-layout simulation with Mach. TA �Mach. TA is an accelerated Spice simulator �Digital & mixed-signal circuits �Analyze timing effects pre- and post-layout �SPICE netlists with parasitic R/C �Execute test vector file to verify functionality �Algorithms support large designs �Partition design, simulate only partitions with changes �Combine time-driven & event-driven operation �Solves linearized models using a proprietary highperformance, graph-theory based, matrix solution algorithm

Mach TA flow diagram SPICE netlist $ADK/technology/mta/tsmc 035

Prepare Calibre-extracted netlist for Mach TA (file. pex. netlist) � In file. pex. netlist, insert model definitions and VDD/GND voltage source functions after comment header: * File: m 7. pex. netlist * Created: Thu Nov 15 15: 25: 56 2007 * Program "Calibre x. RC" * Version "v 2005. 2_9. 14". model n nmos. model p pmos Vvdd VDD 0 5 Vgnd GND 0 0 � Delete (or comment out with * in 1 st column). subcircuit statement and any continuation lines (for long statement): *. subckt modulo 7 CLK Q[1] CLEARBAR I[1] Q[0] I[0] Q[2] *+ L_CBAR I[2] GND VDD � Change. ends to. END near end of file

Post-layout simulation with Mach TA �Invoke Mach TA: ana - command file to initialize Anacad SW mta –ezw –t $ADK/technology/mta/tsmc 035 count 4. sp Transistor calibration files for this technology Generate waveform database & display in EZwave Netlist, modified as on previous slide Other options: -do file (execute commands from file. do – instead of design. spdo -donot (run without simulating – compile only) -b (run in batch mode – no GUI – output to console)

Sample Mach TA “dofile” (transient analysis) Signals to observe in EZwave plot v(clk) v(q[2]) v(q[1]) v(q[0]) measure rising TRIG v(clk) VAL=2. 5 v RISE=1 TARG v(q[0]) VAL=2. 5 v l load l reset Measure time from rising edge of clk (TRIGger) h count to 1 st rising edge of q[0] (TARGet) - voltages l clk run 5 ns h reset Drive signals low/high (Lsim format) h clk run 5 ns l clk Simulate for 5 ns run 5 ns h clk run 5 ns Command to execute: dofile. do

EZwaveform viewer (results for previous dofile) Double-click signal name to display.

Alternative Mach TA “dofile” (same result as previous example) plot v(clk) v(q[2]) v(q[1]) v(q[0]) measure rising TRIG v(clk) VAL=2. 5 v RISE=1 TARG v(q[0]) VAL=2. 5 v vpulse Vclk 0 pulse(0 3. 3 10 n. 05 n 10 n 20 n) v-levels delay rise fall width period l load l reset Nodes to which h count source connected Periodic pulses run 5 ns h reset Voltage source name run 200 ns

Mach TA – test vector file �Verify design functionality/behavior �apply test vectors �capture outputs �compare outputs to expected result �use vectors/outputs from behavioral simulation �Command to execute a test vector file: run –tvend tvfile. tv test vector file (next slide)

Test vector file format # Test vector file for modulo 7 counter CODEFILE UNITS ps RISE_TIME 50 signal order within vectors Header FALL_TIME 50 INPUTS clk, reset, load, count, i[2], i[1], i[0]; OUTPUTS q[2] (to=max), q[1] (to=max), q[0] (to=max); CODING(ROM) Vector format RADIX <11113>3; @0 <01105>X; Sample 5 fs before next vector @2000 <00105>0; @7000 <01105>0; @10000 <11105>5; @20000 <01015>5; Vectors: @time <input_vector>expected_output @30000 <11015>6; @40000 <01015>6; @50000 <11015>0; @60000 <01015>0; …. . END Test vectors derived from behavioral simulation results

Behavioral simulation listing Corresponding Mach TA test vector file

Alternate test vector file (clock generated separately by voltage source) vpulse vclk 0 pulse(0 3. 3 10 n. 5 n 10 n 20 n) Can mix other simulation commands with test vector application.

Mach TA has been replaced by ADi. T • Fast-SPICE simulator • Analog & mixed-signal • 10 X to 100 X faster than other SPICE simulators • Integrated with Questa

Top level layout design flow** �Create a symbol for each core block (adk_daic) �Create a chip-level schematic from core blocks and pads (adk_daic) �Generate design viewpoints (adk_dve) �Create a layout cell for the chip(adk_ic) �Place core logic blocks from the schematic �Generate a pad frame �Move/alter core blocks to simplify routing �Route pads to core blocks �Design rule check & fix problems �Generate mask data ** Refer to on-line tutorials by Yan/Xu and by Dixit/Poladia

Chip-level schematic (1) �Generate a symbol for each “core” logic block �In DA-IC, open the schematic (eg. modulo 7) �Select: Miscellaneous > Generate Symbol �Add “phy_comp” property to the symbol �Select the body of the symbol �From the popup menu: Properties > Add �Enter property name: phy_comp �Enter property value: mod 7 b (layout cell name for the block created in IC Station) �Check & save Example on next slide

Symbol with phy_comp property Layout cell is “mod 7 b” for logic schematic “modulo 7”

Chip-level schematic (2) �In DA-IC, create a schematic for the chip �Instantiate core blocks �Menu pallete: Add > Instance �Select and place generated symbol �Add pads from ADK Library>Std. Cells>Pads >tsmc 035 : In, Out, Bi. Dir, VDD, GND �Wire pads to logic blocks and connectors �Assign pin numbers, if known �Change pad instance name to PINdd (dd = 2 -digit pin #) �Check & save �Create design viewpoints with adk_dve Example on next slide

Assigning PAD pin numbers Change instance name property on pads to PINxx xx = 2 -digit pin number (01 – 40 for Tiny Chip package) Place pad on chip pin 01 Default instance names

Top-level schematic for “modulo 7” chip VDD/GND Pads Hierarchical connectors on “Pad” pins Instance name = PINxx (chip pin #) Core block Wire block I/O pins to pad signal pins

Chip layout �Start IC Station (adk_ic) & create a new layout cell �enter cell name �logic source is “layout” viewpoint of chip schematic �same library, process file, rules file, and options as standard cell layout �Open the schematic �ADK Edit menu: Logic Source > Open �In the schematic, select all core cells (but not pads) �Place the cells: Place > Inst �Generate the pad frame �Top menu bar: ADK > Generate Padframe > tsmc 035

Chip layout (2) �Move, rotate, flip core logic cells as desired to make routing easier �BUT - DO NOT EDIT OR MOVE PAD CELLS �Autoroute all connections �Select autoroute all on P&R menu �Click “options” on prompt bar, and unselect “Expand Channels” (prevents pads from being moved) �Add missing VDD/GND wires, if necessary �Autorouter might only route 1 VDD/GND wire, even if multiple VDD/GND pads �Manually add others: Objects>Add>Path �VDD/GND net width = 50 �VDD/GND net vias = 6 x 6 (copy an existing via)

Modulo-7 counter in pad frame