Computer System Design Processor Design Lecture 10 Memory

Computer System Design (Processor Design( Lecture 10 : Memory Technology CE 240 -334 Suntiamorntut 2/1999

Where are we now? CE 240 -334 Suntiamorntut 2/1999

Technology Trends CE 240 -334 Suntiamorntut 2/1999

Expanded View of the Memory System CE 240 -334 Suntiamorntut 2/1999

Memory Hierarchy of a Modern Computer System CE 240 -334 Suntiamorntut 2/1999

How is the hierarchy managed? CE 240 -334 Suntiamorntut 2/1999

Logic Diagram of a Typical SRAM CE 240 -334 Suntiamorntut 2/1999

Typical of SRAM Timing CE 240 -334 Suntiamorntut 2/1999

Classical DRAM Organization (square( CE 240 -334 Suntiamorntut 2/1999

Logical Diagram of a Typical DRAM CE 240 -334 Suntiamorntut 2/1999

Art of Memory System Design CE 240 -334 Suntiamorntut 2/1999

Example : 1 KB Direct Mapped Cache with 32 B Blocks CE 240 -334 Suntiamorntut 2/1999

Example : Fully Associative CE 240 -334 Suntiamorntut 2/1999

A Two-way Set Associative Cache CE 240 -334 Suntiamorntut 2/1999

Disadvantage of Set Associative Cache CE 240 -334 Suntiamorntut 2/1999

How do you design a cache? CE 240 -334 Suntiamorntut 2/1999

1 KB Direct mapped Cache, 32 B blocks CE 240 -334 Suntiamorntut 2/1999

Improving Cache Performance : 3 general options CE 240 -334 Suntiamorntut 2/1999

Where can a block be placed in the upper level? CE 240 -334 Suntiamorntut 2/1999

Example CE 240 -334 Suntiamorntut 2/1999