Computer Organization Instruction Sets MIPS Reading 2 3

Computer Organization Instruction Sets: MIPS Reading: 2. 3 -2. 6 IDT 79 R 4600 Orion Portions of these slides are derived from: Textbook figures © 1998 Morgan Kaufmann Publishers all rights reserved Tod Amon's COD 2 e Slides © 1998 Morgan Kaufmann Publishers all rights reserved Dave Patterson’s CS 152 Slides - Fall 1997 © UCB Rob Rutenbar’s 18 -347 Slides - Fall 1999 CMU Instruction Sets: MIPS Feb. 2005 other sources as noted 1

Outline - Instruction Sets } Instruction Set Overview } MIPS Instruction Set } Overview } Registers and Memory } MIPS Instructions } Software Concerns } Summary Feb. 2005 Instruction Sets: MIPS 2

MIPS Architecture - Applications } Workstations/Servers } SGI Workstations } SGI Servers } Embedded Applications - examples } } } } } Network Routers Laser Printers Digital Cameras Game Consoles: Sony PS 2 / Nintendo 64 Personal Digital Assistants Image Source: www. aibo-life. com Sony AIBO & QRIO Robots http: //www. answers. com/topic/mips-architecture http: //biz. yahoo. com/prnews/050127/sfth 054_1. html http: //www. us. design-reuse. com/news 8544. html Feb. 2005 Instruction Sets: MIPS 3

MIPS Design Principles 1. Simplicity Favors Regularity 2. Smaller is Faster 3. Good Design Makes Good Compromises 4. Make the Common Case Fast Feb. 2005 Instruction Sets: MIPS 4

Outline - Instruction Sets } Instruction Set Overview } MIPS Instruction Set } Overview } Registers and Memory } MIPS Instructions } Software Concerns } Summary Feb. 2005 Instruction Sets: MIPS 5

MIPS Registers and Memory 32 bits R 0 R 1 R 2 R 30 R 31 32 General Purpose Registers PC = 0 x 0000001 C 0 x 00000004 0 x 00000008 0 x 0000000 C 0 x 00000010 0 x 00000014 0 x 00000018 0 x 0000001 C 0 xfffffff 4 0 xfffffffc Registers Memory 4 GB Max (Typically 64 MB-1 GB) Feb. 2005 Instruction Sets: MIPS 6

MIPS Registers } Fast access to program data } Register R 0/$0/$zero: hardwired to constant zero } Register names: } $0 -$31 or R 0 -R 31 } Specialized names based on usage convention • • • $zero ($0) - always zero $s 0 -$s 7 ($16 -$23) - “saved” registers $t 0 -$t 7 ($8 -$15) - “temporary” registers $sp - stack pointer Other special-purpose registers Feb. 2005 Instruction Sets: MIPS 7

MIPS Registers and Usage Feb. 2005 Instruction Sets: MIPS 8

More about MIPS Memory Organization } Two views of memory: } 232 bytes with addresses 0, 1, 2, …, 232 -1 } 230 4 -byte words* with addresses 0, 4, 8, …, 232 -4 Not all architectures require this } Both views use byte addresses } Word address must be multiple of 4 (aligned) 8 bits 0 x 00000001 0 x 00000002 0 x 00000003 32 bits 0 x 00000004 0 x 00000008 0 x 0000000 C 0 1 2 3 *Word sizes vary in other architectures Feb. 2005 Instruction Sets: MIPS 9

Outline - Instruction Sets } Instruction Set Overview } MIPS Instruction Set } Overview } Registers and Memory } MIPS Instructions } Software Concerns } Summary Feb. 2005 Instruction Sets: MIPS 10

MIPS Instructions } All instructions exactly 32 bits wide } Different formats for different purposes } Similarities in formats ease implementation 6 bits 5 bits op rs rt rd 6 bits 5 bits 16 bits op rs rt offset shamt funct 6 bits 26 bits op address Feb. 2005 6 bits Instruction Sets: MIPS R-Format I-Format J-Format 11

MIPS Instruction Types } Arithmetic & Logical - manipulate data in registers add $s 1, $s 2, $s 3 or $s 3, $s 4, $s 5 $s 1 = $s 2 + $s 3 = $s 4 OR $s 5 } Data Transfer - move register data to/from memory lw $s 1, 100($s 2) $s 1 = Memory[$s 2 + 100] sw $s 1, 100($s 2) Memory[$s 2 + 100] = $s 1 } Branch - alter program flow beq $s 1, $s 2, 25 if ($s 1==$s 1) PC = PC + 4*25 Feb. 2005 Instruction Sets: MIPS 12

MIPS Arithmetic & Logical Instructions } Instruction usage (assembly) add dest, src 1, src 2 sub dest, src 1, src 2 and dest, src 1, src 2 dest=src 1 + src 2 dest=src 1 - src 2 dest=src 1 AND src 2 } Instruction characteristics } Always 3 operands: destination + 2 sources } Operand order is fixed } Operands are always general purpose registers } Design Principles: } Design Principle 1: Simplicity favors regularity } Design Principle 2: Smaller is faster Feb. 2005 Instruction Sets: MIPS 13

Arithmetic Instruction Examples } C simple addition and assignment C code: A=B+C MIPS code: add $s 0, $s 1, $s 2 } Complex arithmetic assignment: C code: A = B + C + D; E = F - A; MIPS code: add $t 0, $s 1, $s 2 add $s 0, $t 0, $s 3 sub $s 4, $s 5, $s 0 } Compiler keeps track of mapping variables to registers (and, when necessary, memory) Feb. 2005 Instruction Sets: MIPS 14

Arithmetic & Logical Instructions Binary Representation 6 bits 5 bits op rs rt rd 5 bits 6 bits shamt funct } Used for arithmetic, logical, shift instructions } } } op: Basic operation of the instruction (opcode) rs: first register source operand rt: second register source operand rd: register destination operand shamt: shift amount (more about this later) funct: function - specific type of operation } Also called “R-Format” or “R-Type” Instructions Feb. 2005 Instruction Sets: MIPS 15

Arithmetic & Logical Instructions Binary Representation Example } Machine language for add $8, $17, $18 } See reference card for op, funct values 6 bits 5 bits op rs rt rd 0 17 18 8 5 bits 6 bits shamt funct 0 32 000000 10001 10010 01000 00000 100000 Feb. 2005 Instruction Sets: MIPS Decimal Binary 16

MIPS Data Transfer Instructions } Transfer data between registers and memory } Instruction format (assembly) lw $dest, offset($addr) sw $src, offset($addr) load word store word } Uses: } Accessing a variable in main memory } Accessing an array element Feb. 2005 Instruction Sets: MIPS 17

Example - Loading a Simple Variable 8 R 0=0 (constant) R 1 R 2=0 x 10 R 3 R 4 R 5 =R 5 629310 + 0 x 00 0 x 04 0 x 08 0 x 0 c 0 x 10 0 x 14 0 x 18 0 x 1 c Variable X Variable Y Variable Z = 692310 R 31 Registers lw R 5, 8(R 2) Feb. 2005 Instruction Sets: MIPS Memory 18

Data Transfer Example - Array Variable 12=0 xc R 0=0 (constant) R 1 R 2=0 x 08 R 3 R 4 R 5=105 + Base Address 0 x 00 0 x 04 0 x 08 0 x 0 c 0 x 10 0 x 14 0 x 18 0 x 1 c a[0] a[1] a[2] a[3]=105 a[3] a[4] R 30 R 31 Registers C Program: Assembly: Feb. 2005 int a[5]; a[3] = z; scaled offset sw $5, 12($2) Instruction Sets: MIPS Memory 19

Data Transfer Instructions Binary Representation 6 bits 5 bits 16 bits op rs rt offset } Used for load, store instructions } } op: Basic operation of the instruction (opcode) Address rs: first register source operand source for sw rt: second register source operand destination for lw offset: 16 -bit signed address offset (-32, 768 to +32, 767) } Also called “I-Format” or “I-Type” instructions Feb. 2005 Instruction Sets: MIPS 20

I-Format vs. R-Format Instructions } Compare with R-Format 6 bits 5 bits op rs rt rd 6 bits 5 bits 16 bits op rs rt offset 6 bits shamt funct R-Format I-Format Note similarity! Feb. 2005 Instruction Sets: MIPS 21

I-Format Example } Machine language for lw $9, 1200($8) == lw $t 1, $1200($t 0) 6 bits 5 bits 16 bits op rs rt offset 35 8 9 1200 100011 01000 01001 Feb. 2005 0000010010110000 Instruction Sets: MIPS Decimal Binary 22

MIPS Conditional Branch Instructions } Conditional branches allow decision making beq R 1, R 2, LABEL bne R 3, R 4, LABEL if R 1==R 2 goto LABEL if R 3!=R 4 goto LABEL } Example C Code L 1: Assembly L 1: Feb. 2005 if (i==j) goto L 1; f = g + h; f = f - i; beq $s 3, $s 4, L 1 add $s 0, $s 1, $s 2 sub $s 0, $s 3 Instruction Sets: MIPS 23

Example: Compiling C if-then-else } Example C Code if (i==j) f = g + h; else f = g - h; Assembly bne $s 3, $s 4, Else add $s 0, $s 1, $s 2 j Exit; # new: unconditional jump sub $s 0, $s 3 Else: Exit: } New Instruction: Unconditional jump j LABEL # goto Label Feb. 2005 Instruction Sets: MIPS 24

Binary Representation - Branch 6 bits 5 bits 16 bits op rs rt offset } Branch instructions use I-Format } offset is added to PC when branch is taken beq r 0, r 1, offset Conversion to word offset has the effect: if (r 0==r 1) pc = pc + 4 + (offset << 2) else pc = pc + 4; } Offset is specified in instruction words (why? ) } What is the range of the branch target addresses? Feb. 2005 Instruction Sets: MIPS 25

Branch Example } Machine language for $19 PC beq $s 3, $s 4, L 1 PC+4 add $s 0, $s 1, $s 2 Target L 1: sub $s 0, $s 3 of beq 1 -instruction offset 6 bits 5 bits 16 bits op rs rt offset 4 19 20 1 000100 10011 10100 Feb. 2005 $20 000000001 Instruction Sets: MIPS Decimal Binary 26

Comparisons - What about <, <=, >, >=? } bne, beq provide equality comparison } slt provides magnitude comparison slt $t 0, $s 3, $s 4 condition register # if $s 3<$s 4 $t 0=1; # else $t 0=0; } Combine with bne or beq to branch: slt $t 0, $s 3, $s 4 bne $t 0, $zero, Less # if (a<b) # goto Less; } Why not include a blt instruction in hardware? } Supporting in hardware would lower performance } Assembler provides this function if desired (by generating the two instructions) Feb. 2005 Instruction Sets: MIPS 27

Binary Representation - Jump 6 bits 26 bits op address } Jump Instruction uses J-Format (op=2) } What happens during execution? PC = PC[31: 28] : (IR[25: 0] << 2) Concatenate upper 4 bits of PC to form complete 32 -bit address Feb. 2005 Conversion to word offset Instruction Sets: MIPS 28

Jump Example } Machine language for Assume L 5 is at address 0 x 00400020 and j L 5 lower 28 PC <= 0 x 03 FFFFFF bits >>2 Feb. 2005 6 bits 26 bits op address 2 0 x 0100008 000010 000001000000001000 Instruction Sets: MIPS 0 x 0100008 Decimal/Hex Binary 29

Constants / Immediate Instructions } Small constants are used quite frequently (50% of operands) e. g. , A = A + 5; B = B + 1; C = C - 18; } MIPS Immediate Instructions (I-Format): addi $29, 4 slti $8, $18, 10 andi $29, 6 ori $29, 4 Arithmetic instructions sign-extend immed. Logical instructions don’t sign extend immed. } Allows up to 16 -bit constants } How do you load just a constant into a register? ori $5, $zero, 666 Feb. 2005 Instruction Sets: MIPS 30

Why are Immediates only 16 bits? } Because 16 bits fits neatly in a 32 -bit instruction } Because most constants are small (i. e. < 16 bits) } Design Principle 4: Make the Common Case Fast Feb. 2005 Instruction Sets: MIPS 31

MIPS Logical Instructions } and, andi - bitwise AND } or, ori - bitwise OR } Example $s 0 110111110100100100011110101 $s 1 1111000011110000 and $s 2 110100000100000011110000 ori $s 3, s 2, 252 (25210) 00000000000011111100 $s 3 $s 2, $s 0, $s 1 110100000100000011111100 Feb. 2005 Instruction Sets: MIPS 32

Logical Operations - Applications } Masking - clear, set or test } Individual bits } Groups of bits Feb. 2005 Instruction Sets: MIPS 33

Larger Constants } Immediate operations provide for 16 -bit constants } What about when we need larger constants? } Use "load upper immediate - lui” (I-Format) lui $t 0, 10101010 filled with zeros $t 0 10101010 (original contents) 00000000 } Then use ori to fill in lower 16 bits: ori $t 0, 10101010 $t 0 10101010 Feb. 2005 10101010 00000000 Instruction Sets: MIPS 34

MIPS Shift Instructions } MIPS Logical Shift Instructions } Shift left: sll (shift-left logical) instruction } Right shift: srl (shift-right logical) instruction $s 0 110111110100100100011110101 sll $s 1, $s 0, 8 Zeros shift in $s 1 0101101001001000111101010000 srl $s 2, $s 1, 4 Zeros shift in $s 2 00000101101001001000111101010000 Feb. 2005 Instruction Sets: MIPS 35

Shift Instruction Encodings 6 bits 5 bits 6 bits op rs rt rd shamt funct sll 0 rs rt rd shamt 0 srl 0 rs rt rd shamt 6 unused } Applications } Bitfield access (see book) } Multiplication / Division by power of 2 } Example: array access sll $t 0, $t 1, 2 # $t 0=$t 1*4 add $t 3, $t 1, $t 2 lw $t 3, 0($t 3) Feb. 2005 Instruction Sets: MIPS 36

Summary - MIPS Instruction Set } Three instruction formats } Similarities in formats ease implementation 6 bits 5 bits op rs rt rd 6 bits 5 bits 16 bits op rs rt offset shamt funct 6 bits 26 bits op address Feb. 2005 6 bits Instruction Sets: MIPS R-Format I-Format J-Format 37

Instruction Sets - Overview } Instruction Set Overview } MIPS Instruction Set } Overview } Registers and Memory } Instructions } Software Concerns } } } Compiling C Constructs Procedures (Subroutines) and Stacks Example: Internet Worms Compiling, Linking, and Loading Example: String Processing / SPIM Demo Feb. 2005 Instruction Sets: MIPS 38