Computer Organization Design Microcode for Control Sec 5
- Slides: 21
Computer Organization & Design Microcode for Control Sec. 5. 7 (CDROM) Appendix C (CDROM) / 3055 -05 / pdf / lec_3 a_notes. pdf 1
The Processor: Datapath & Control • • We're ready to look at an implementation of the MIPS Simplified to contain only: – memory-reference instructions: lw, sw – arithmetic-logical instructions: add, sub, and, or, slt – control flow instructions: beq, j • Generic Implementation: – – • use the program counter (PC) to supply instruction address get the instruction from memory read registers use the instruction to decide exactly what to do All instructions use the ALU after reading the registers Why? memory-reference? arithmetic? control flow? 2
Control • • • e. g. , what should the ALU do with this instruction Example: lw $1, 100($2) 35 2 1 op rs rt 16 bit offset ALU control input 000 001 010 111 • 100 AND OR add subtract set-on-less-than Why is the code for subtract 110 and not 011? 3
Control • Must describe hardware to compute 3 -bit ALU control input – given instruction type 00 = lw, sw ALUOp 01 = beq, computed from instruction type 11 = arithmetic – function code for arithmetic • Describe it using a truth table (can turn into gates): 4
Control 5
Implementing the Control • Value of control signals is dependent upon: – what instruction is being executed – which step is being performed • Use the information we’ve accumulated to specify a finite state machine – specify the finite state machine graphically, or – use microprogramming • Implementation can be derived from specification 6
Graphical Specification of FSM • How many state bits will we need? 10 states, < 2^4 4 bits 7
Finite State Machine for Control • Implementation: Control Logic Data path Instruction Register Opcode Field 8
PLA Implementation • If I picked a horizontal or vertical line could you explain it? Op 5 Op 4 Op 3 Op 2 Op 1 Op 0 State 3 State 2 State 1 State 0 PCWrite. Cond Ior. D Mem. Read Mem. Write IRWrite Memto. Reg PCSource 1 PCSource 0 ALUop 1 ALUop 0 ALUsrce 1 ALUsrce 0 ALUsrce Reg. Write Reg. Dst Next. State 3 Next. State 2 Next. State 1 Next. State 0 9
PLA Implementation Orange dots are AND gates • Red color shows lines that are "high" or "1" Op 5 = 1 Op 4 = 0 Op 3 = 0 Op 2 = 0 Op 1 = 1 Op 0 = 0 State 3 = 0 State 2 = 0 State 1 = 0 State 0 = 1 State 1 (0001) is followed by state 2 (0010) if Op = 100010, with ALUsrce 0 and ALUsrce 1 set to "1" (true). Grey dots are OR gates, 1 or hi-Z "1" Output PCWrite = 0 PCWrite. Cond = 0 Ior. D = 0 Mem. Read = 0 Mem. Write = 0 IRWrite = 0 Memto. Reg = 0 PCSource 1 = 0 PCSource 0 = 0 ALUop 1 = 0 ALUop 0 = 0 ALUsrce 1 =1 ALUsrce 0 = 1 ALUsrce = 0 Reg. Write = 0 Reg. Dst = 0 Next. State 3 = 0 Next. State 2 = 0 Next. State 1 = 1 Next. State 0 = 0 10
ROM Implementation • • ROM = "Read Only Memory" – values of memory locations are fixed ahead of time A ROM can be used to implement a truth table – if the address is m-bits, we can address 2 m entries in the ROM. – our outputs are the bits of data that the address points to. m n 0000011100 0101100 0111000000 1010001 1100110 1110111 m is the "height", and n is the "width" 11
ROM Implementation • • How many inputs are there? 6 bits for opcode, 4 bits for state = 10 address lines (i. e. , 210 = 1024 different addresses) How many outputs are there? 16 datapath-control outputs, 4 state bits = 20 outputs • ROM is 210 x 20 = 20 K bits • Rather wasteful, since for lots of the entries, the outputs are the same — i. e. , opcode is often ignored (and a rather unusual size) 12
ROM vs PLA • Break up the table into two parts — 4 state bits tell you the 16 outputs, 24 x 16 bits of ROM — 10 bits tell you the 4 next state bits, 210 x 4 bits of ROM — Total: 4. 3 K bits of ROM • PLA is much smaller — can share product terms — only need entries that produce an active output — can take into account don't cares • Size is (#inputs #product-terms) + (#outputs #product-terms) For this example = (10 x 17)+(20 x 17) = 460 PLA cells • PLA cells usually about the size of a ROM cell (slightly bigger) 13
Another Implementation Style • Complex instructions: the "next state" is often current state + 1 Control Unit PLA or ROM Data path State Address Select Logic Instruction Register Opcode Field 14
Details State Add 1 Addr. Ctl Dispatch ROM 2 Dispatch ROM 1 Instruction Register Opcode Field Address Select Logic 15
Microprogramming Control Unit Microcode Memory Data path Microprogram Counter Address Select Logic Instruction Register Opcode Field • What are the “microinstructions” ? 16
Microprogramming • A specification methodology – appropriate if hundreds of opcodes, modes, cycles, etc. – signals specified symbolically using microinstructions • • Will two implementations of the same architecture have the same microcode? What would a microassembler do? 17
Microinstruction format 18
Maximally vs. Minimally Encoded • No encoding: – 1 bit for each datapath operation – faster, requires more memory (logic) – used for Vax 780 — an astonishing 400 K of memory! • Lots of encoding: – send the microinstructions through logic to get control signals – uses less memory, slower • Historical context of CISC: – Too much logic to put on a single chip with everything else – Use a ROM (or even RAM) to hold the microcode – It’s easy to add new instructions 19
Microcode: Trade-offs • Distinction between specification and implementation is sometimes blurred • Specification Advantages: – Easy to design and write – Design architecture and microcode in parallel • Implementation (off-chip ROM) Advantages – Easy to change since values are in memory – Can emulate other architectures – Can make use of internal registers • Implementation Disadvantages, SLOWER now that: – Control is implemented on same chip as processor – ROM is no longer faster than RAM – No need to go back and make changes 20
The Big Picture Initial Representation Sequencing Control Logic Representation Implementation Technique Finite State Diagram Microprogram Explicit Next-State Function Microprogram Counter + Dispatch ROMS Logic Equation Truth Tables Programmable Logic Array Read Only Memory 21
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