Computer Organization CS 224 Fall 2011 Chapter 2

Computer Organization CS 224 Fall 2011 Chapter 2 c With thanks to M. J. Irwin, D. Patterson, and J. Hennessy for some lecture slide contents CS 224 Fall 2011 Chapter 2 c

Branch instructions specify Opcode, two registers, target address Most branch targets are near branch Forward or backward PC-relative addressing Target address = PC + offset × 4 PC already incremented by 4 by this time CS 224 Fall 2011 Chapter 2 c § 2. 10 MIPS Addressing for 32 -Bit Immediates and Addresses Branch Addressing

Other Control Flow Instructions MIPS also has an unconditional branch instruction or jump instruction: j label #go to label Instruction Format (J Format): CS 224 Fall 2011 Chapter 2 c

Jump Addressing Jump (j and jal) targets could be anywhere in text segment Encode full address in instruction Pseudo-Direct jump addressing Target address = PC 31… 28 : (address × 4) CS 224 Fall 2011 Chapter 2 c

Target Addressing Example Loop code from earlier example Assume Loop at location 80000 $t 1, $s 3, 2 80000 0 0 19 9 2 0 add $t 1, $s 6 80004 0 9 22 9 0 32 lw $t 0, 0($t 1) 80008 35 9 8 0 bne $t 0, $s 5, Exit 80012 5 8 21 2 addi $s 3, 1 80016 8 19 19 1 j 80020 2 Loop: sll Loop Exit: … CS 224 Fall 2011 Chapter 2 c 80024 20000

Aside: Branching Far Away What if the branch destination is further away than can be captured in 16 bits? The assembler comes to the rescue – it inserts an unconditional jump to the branch target and inverts the condition beq $s 0, $s 1, L 1_far becomes bne $s 0, $s 1, L 2 j L 1_far L 2: CS 224 Fall 2011 Chapter 2 c

Addressing Mode Summary CS 224 Fall 2011 Chapter 2 c

MIPS Organization So Far Processor Memory Register File src 1 addr src 2 addr dst addr write data 5 5 5 1… 1100 src 1 data 32 32 registers ($zero - $ra) read/write addr src 2 32 data 32 32 32 bits branch offset 32 PC 32 Add 4 230 words 32 Add read data 32 32 32 write data 32 32 32 ALU 32 32 4 0 5 1 32 bits byte address (big Endian) CS 224 Fall 2011 Chapter 2 c 6 2 7 3 0… 1100 0… 1000 0… 0100 0… 0000 word address (binary)

MIPS Instruction Classes Distribution Frequency of MIPS instruction classes for SPEC 2006 Instruction Class Frequency Integer Ft. Pt. Arithmetic 16% 48% Data transfer 35% 36% Logical 12% 4% Cond. Branch 34% 8% Jump 2% 0% CS 224 Fall 2011 Chapter 2 c

Two processors sharing an area of memory P 1 writes, then P 2 reads Data race if P 1 and P 2 don’t synchronize - Result depends of order of accesses Hardware support required Atomic read/write memory operation No other access to the location allowed between the read and write Could be a single instruction E. g. , atomic swap of register ↔ memory Or an atomic pair of instructions CS 224 Fall 2011 Chapter 2 c § 2. 11 Parallelism and Instructions: Synchronization

Atomic Exchange Support Need hardware support for synchronization mechanisms to avoid data races where the results of the program can change depending on how events happen to occur Atomic exchange (atomic swap) – interchanges a value in a register for a value in memory atomically, i. e. , as one operation (instruction) ll Two memory accesses from different threads to the same location, and at least one is a write Implementing an atomic exchange would require both a memory read and a memory write in a single, uninterruptable instruction. An alternative is to have a pair of specially configured instructions $t 1, 0($s 1) sc $t 0, 0($s 1) CS 224 Fall 2011 Chapter 2 c #load linked #store conditional

Atomic Exchange with ll and sc If the contents of the memory location specified by the ll are changed before the sc to the same address occurs, the sc fails (returns a zero) try: ll sc add $t 0, $zero, $s 4 #$t 0=$s 4 (exchange value) $t 1, 0($s 1) #load memory value to $t 1 $t 0, 0($s 1) #try to store exchange #value to memory, if fail #$t 0 will be 0 beq $t 0, $zero, try #try again on failure add $s 4, $zero, $t 1 #load value in $s 4 If the value in memory between the ll and the sc instructions changes, then sc returns a 0 in $t 0 causing the code sequence to try again. CS 224 Fall 2011 Chapter 2 c

C program machine code CS 224 Fall 2011 Chapter 2 c § 2. 12 Translating and Starting a Program The C Code Translation Hierarchy

Assembler Pseudoinstructions Most assembler instructions represent machine instructions one-to-one Pseudoinstructions: figments of the assembler’s imagination move $t 0, $t 1 → add $t 0, $zero, $t 1 blt $t 0, $t 1, L → slt $at, $t 0, $t 1 bne $at, $zero, L $at (register 1): assembler temporary CS 224 Fall 2011 Chapter 2 c

Producing an Object Module Assembler (or compiler) translates program into machine instructions Provides information for building a complete program from the pieces Header: Text described contents of object module segment: translated instructions Static data segment: data allocated for the life of the program Relocation info: for contents that depend on absolute location of loaded program Symbol Debug CS 224 Fall 2011 Chapter 2 c table: global definitions and external refs info: for associating with source code

Linking Object Modules Produces an executable image 1. Merges segments 2. Resolve labels (determine their addresses) 3. Patch location-dependent and external refs Could leave location dependencies for fixing by a relocating loader But with virtual memory, no need to do this Program can be loaded into absolute location in virtual memory space CS 224 Fall 2011 Chapter 2 c

Loading a Program Load from image file on disk into memory 1. Read header to determine segment sizes 2. Create virtual address space 3. Copy text and initialized data into memory - Or set page table entries so they can be faulted in 4. Set up arguments on stack 5. Initialize registers (including $sp, $fp, $gp) 6. Jump to startup routine - Copies arguments to $a 0, … and calls main - When main returns, do exit syscall CS 224 Fall 2011 Chapter 2 c

Dynamic Linking Only link/load library procedure when it is called Requires procedure code to be relocatable Avoids image bloat caused by static linking of all (transitively) referenced libraries Automatically picks up new library versions CS 224 Fall 2011 Chapter 2 c

Lazy Linkage Indirection table Stub: loads routine ID, jumps to linker/loader Linker/loader code Dynamically mapped code CS 224 Fall 2011 Chapter 2 c

Starting Java Applications Simple portable instruction set for the JVM Compiles bytecodes of “hot” methods into native code for host machine CS 224 Fall 2011 Chapter 2 c Interprets bytecodes

Illustrates use of assembly instructions for a C bubble sort function Swap procedure (leaf) void swap(int v[], int k) { int temp; temp = v[k]; v[k] = v[k+1]; v[k+1] = temp; } v in $a 0, k in $a 1, temp in $t 0 CS 224 Fall 2011 Chapter 2 c § 2. 13 A C Sort Example to Put It All Together C Sort Example

The Procedure Swap swap: sll $t 1, $a 1, 2 # $t 1 = k * 4 add $t 1, $a 0, $t 1 # $t 1 = v+(k*4) # (address of v[k]) lw $t 0, 0($t 1) # $t 0 (temp) = v[k] lw $t 2, 4($t 1) # $t 2 = v[k+1] sw $t 2, 0($t 1) # v[k] = $t 2 (v[k+1]) sw $t 0, 4($t 1) # v[k+1] = $t 0 (temp) jr $ra # return to calling routine CS 224 Fall 2011 Chapter 2 c

The Sort Procedure in C Non-leaf (calls swap) void sort (int v[], int n) { int i, j; for (i = 0; i < n; i += 1) { for (j = i – 1; j >= 0 && v[j] > v[j + 1]; j -= 1) { swap(v, j); } } } v in $a 0, n in $a 1, i in $s 0, j in $s 1 CS 224 Fall 2011 Chapter 2 c

The Procedure Body move for 1 tst: slt beq addi for 2 tst: slti bne sll add lw lw slt beq move jal addi j exit 2: addi j CS 224 Fall 2011 Chapter 2 c $s 2, $a 0 $s 3, $a 1 $s 0, $zero $t 0, $s 3 $t 0, $zero, exit 1 $s 1, $s 0, – 1 $t 0, $s 1, 0 $t 0, $zero, exit 2 $t 1, $s 1, 2 $t 2, $s 2, $t 1 $t 3, 0($t 2) $t 4, 4($t 2) $t 0, $t 4, $t 3 $t 0, $zero, exit 2 $a 0, $s 2 $a 1, $s 1 swap $s 1, – 1 for 2 tst $s 0, 1 for 1 tst # # # # # # save $a 0 into $s 2 Move save $a 1 into $s 3 params i = 0 $t 0 = 0 if $s 0 ≥ $s 3 (i ≥ n) Outer loop go to exit 1 if $s 0 ≥ $s 3 (i ≥ n) j = i – 1 $t 0 = 1 if $s 1 < 0 (j < 0) go to exit 2 if $s 1 < 0 (j < 0) $t 1 = j * 4 Inner loop $t 2 = v + (j * 4) $t 3 = v[j] $t 4 = v[j + 1] $t 0 = 0 if $t 4 ≥ $t 3 go to exit 2 if $t 4 ≥ $t 3 1 st param of swap is v (old $a 0) Pass 2 nd param of swap is j params call swap procedure & call j –= 1 Inner loop jump to test of inner loop i += 1 Outer loop jump to test of outer loop

The Full Procedure sort: exit 1: addi $sp, – 20 sw $ra, 16($sp) sw $s 3, 12($sp) sw $s 2, 8($sp) sw $s 1, 4($sp) sw $s 0, 0($sp) … … lw $s 0, 0($sp) lw $s 1, 4($sp) lw $s 2, 8($sp) lw $s 3, 12($sp) lw $ra, 16($sp) addi $sp, 20 jr $ra CS 224 Fall 2011 Chapter 2 c # make room on stack for 5 registers # save $ra on stack # save $s 3 on stack # save $s 2 on stack # save $s 1 on stack # save $s 0 on stack # procedure body # # # # restore $s 0 from stack restore $s 1 from stack restore $s 2 from stack restore $s 3 from stack restore $ra from stack restore stack pointer return to calling routine

Compiler Benefits Comparing performance for bubble (exchange) sort To sort 100, 000 words with the array initialized to random values on a Pentium 4 with a 3. 06 clock rate, a 533 MHz system bus, with 2 GB of DDR SDRAM, using Linux version 2. 4. 20 gcc opt Relative performance Clock cycles (M) Instr count (M) CPI None 1. 00 158, 615 114, 938 1. 38 O 1 (medium) 2. 37 66, 990 37, 470 1. 79 O 2 (full) 2. 38 66, 521 39, 993 1. 66 O 3 (proc mig) 2. 41 65, 747 44, 993 1. 46 The unoptimized code has the best CPI, the O 1 version has the lowest instruction count, but the O 3 version is the fastest. Why? CS 224 Fall 2011 Chapter 2 c

Effect of Compiler Optimization Compiled with gcc for Pentium 4 under Linux CS 224 Fall 2011 Chapter 2 c

Sorting in C versus Java Comparing performance for two sort algorithms in C and Java (Bubble. Sort vs. Quicksort) The JVM/JIT is Sun/Hotspot version 1. 3. 1/1. 3. 1 Method Opt Bubble Quick Relative performance Speedup Quick vs. Bubble C Compiler None 1. 00 2468 C Compiler O 1 2. 37 1. 50 1562 C Compiler O 2 2. 38 1. 50 1555 C Compiler O 3 2. 41 1. 91 1955 Java Interpreted 0. 12 0. 05 1050 Java JIT compiler 2. 13 0. 29 338 Observations? CS 224 Fall 2011 Chapter 2 c

Effect of Language and Algorithm CS 224 Fall 2011 Chapter 2 c

Lessons Learned Instruction count and CPI are not good performance indicators in isolation Compiler optimizations are sensitive to the algorithm Java/JIT compiled code is significantly faster than JVM interpreted Comparable to optimized C in some cases Nothing can fix a dumb algorithm! CS 224 Fall 2011 Chapter 2 c

Array indexing involves Multiplying index by element size Adding to array base address Pointers correspond directly to memory addresses Can avoid indexing complexity CS 224 Fall 2011 Chapter 2 c § 2. 14 Arrays versus Pointers Arrays vs. Pointers

Example: Clearing an Array clear 1(int array[], int size) { int i; for (i = 0; i < size; i += 1) array[i] = 0; } move $t 0, $zero loop 1: sll $t 1, $t 0, 2 add $t 2, $a 0, $t 1 clear 2(int *array, int size) { int *p; for (p = &array[0]; p < &array[size]; p = p + 1) *p = 0; } # i = 0 move $t 0, $a 0 # p = & array[0] # $t 1 = i * 4 sll $t 1, $a 1, 2 # $t 1 = size * 4 # $t 2 = add $t 2, $a 0, $t 1 # $t 2 = # &array[i] sw $zero, 0($t 2) # array[i] = 0 # &array[size] loop 2: sw $zero, 0($t 0) # Memory[p] = 0 addi $t 0, 1 # i = i + 1 addi $t 0, 4 slt $t 3, $t 0, $a 1 # $t 3 = slt $t 3, $t 0, $t 2 # $t 3 = # (i < size) bne $t 3, $zero, loop 1 # if (…) # goto loop 1 CS 224 Fall 2011 Chapter 2 c # p = p + 4 #(p<&array[size]) bne $t 3, $zero, loop 2 # if (…) # goto loop 2

Comparison of Array vs. Pointer Versions Multiply “strength reduced” to shift Both versions use sll instead of mul Array version requires shift to be inside loop Part of index calculation for incremented i c. f. incrementing pointer Compiler can achieve same effect as manual use of pointers Induction variable elimination Better to make program clearer and safer Optimizing compilers do these, and many more! See Sec. 2. 15 on CD-ROM CS 224 Fall 2011 Chapter 2 c

ARM: the most popular embedded core Similar basic set of instructions to MIPS ARM MIPS 1985 Instruction size 32 bits Address space 32 -bit flat Data alignment Aligned 9 3 15 × 32 -bit 31 × 32 -bit Memory mapped Date announced Data addressing modes Registers Input/output CS 224 Fall 2011 Chapter 2 c § 2. 16 Real Stuff: ARM Instructions ARM & MIPS Similarities

Compare and Branch in ARM Uses condition codes for result of an arithmetic/logical instruction Negative, zero, carry, overflow are stored in program status Has compare instructions to set condition codes without keeping the result Each instruction can be conditional Top 4 bits of instruction word: condition value Can avoid branches over single instructions, save code space and execution time CS 224 Fall 2011 Chapter 2 c

Instruction Encoding CS 224 Fall 2011 Chapter 2 c

Evolution with backward compatibility 8080 (1974): 8 -bit microprocessor - Accumulator, plus 3 index-register pairs 8086 (1978): 16 -bit extension to 8080 - Complex instruction set (CISC) 8087 (1980): floating-point coprocessor - Adds FP instructions and register stack 80286 (1982): 24 -bit addresses, MMU - Segmented memory mapping and protection 80386 (1985): 32 -bit extension (now IA-32) - Additional addressing modes and operations - Paged memory mapping as well as segments CS 224 Fall 2011 Chapter 2 c § 2. 17 Real Stuff: x 86 Instructions The Intel x 86 ISA

The Intel x 86 ISA Further evolution… i 486 (1989): pipelined, on-chip caches and FPU - Compatible competitors: AMD, Cyrix, … Pentium (1993): superscalar, 64 -bit datapath - Later versions added MMX (Multi-Media e. Xtension) instructions - The infamous FDIV bug Pentium Pro (1995), Pentium II (1997) - New microarchitecture (see Colwell, The Pentium Chronicles) Pentium III (1999) - Added SSE (Streaming SIMD Extensions) and associated registers Pentium 4 (2001) - New microarchitecture - Added SSE 2 instructions CS 224 Fall 2011 Chapter 2 c

The Intel x 86 ISA And further… AMD 64 (2003): extended architecture to 64 bits EM 64 T – Extended Memory 64 Technology (2004) - AMD 64 adopted by Intel (with refinements) - Added SSE 3 instructions Intel Core (2006) - Added SSE 4 instructions, virtual machine support AMD 64 (announced 2007): SSE 5 instructions - Intel declined to follow, instead… Advanced Vector Extension (announced 2008) - Longer SSE registers, more instructions If Intel didn’t extend with compatibility, its competitors would! Technical elegance ≠ market success CS 224 Fall 2011 Chapter 2 c

Basic x 86 Registers CS 224 Fall 2011 Chapter 2 c

Basic x 86 Addressing Modes Two operands per instruction Source/dest operand Second source operand Register Immediate Register Memory Immediate Memory addressing modes Address in register Address = Rbase + displacement Address = Rbase + 2 scale × Rindex (scale = 0, 1, 2, or 3) Address = Rbase + 2 scale × Rindex + displacement CS 224 Fall 2011 Chapter 2 c

x 86 Instruction Encoding Variable length encoding Postfix bytes specify addressing mode Prefix bytes modify operation: - Operand length, repetition, locking, … CS 224 Fall 2011 Chapter 2 c

Implementing IA-32 Complex instruction set makes implementation difficult Hardware translates instructions to simpler microoperations - Simple instructions: 1 -to-1 - Complex instructions: 1 -to-many Microengine similar to RISC Market share makes this economically viable Comparable performance to RISC Compilers avoid the complex instructions CS 224 Fall 2011 Chapter 2 c

Powerful instruction higher performance Fewer instructions required But complex instructions are hard to implement - May slow down all instructions, including simple ones Compilers are good at making fast code from simple instructions Use assembly code for high performance But modern compilers are better at dealing with modern processors More lines of code more errors and less productivity CS 224 Fall 2011 Chapter 2 c § 2. 18 Fallacies and Pitfalls Fallacies

Fallacies Backward compatibility instruction set doesn’t change True: Old instructions never die (Backwards compatibility) But new instructions are certainly added ! x 86 instruction set CS 224 Fall 2011 Chapter 2 c

Concluding Remarks Stored program concept (Von Neumann architecture) means “everything is just bits”—numbers, characters, instructions, etc—all stored in and fetched from memory 4 design principles for instruction set architectures (ISA) Simplicity favors regularity Smaller is faster Make the common case fast Good design demands good compromises CS 224 Fall 2011 Chapter 2 c

Concluding Remarks MIPS ISA offers necessary support for HLL constructs SPEC performance measures instruction execution in benchmark programs Instruction class MIPS examples (HLL examples) SPEC 2006 Int SPEC 2006 FP Arithmetic add, sub, addi (ops used in assignment statements) 16% 48% Data transfer lw, sw, lbu, lhu, sb, lui (references to data structures, e. g. arrays) 35% 36% Logical and, or, nor, andi, ori, sll, srl (ops used in assigment statements) 12% 4% Cond. Branch beq, bne, slti, sltiu (if statements and loops) 34% 8% Jump j, jr, jal (calls, returns, and case/switch) 2% 0% CS 224 Fall 2011 Chapter 2 c