COMPUTER ORGANIZATION By Dr M Khamis Mrs Duaa

COMPUTER ORGANIZATION By Dr. M. Khamis Mrs. Dua’a Al Sinari

COMPUTER ORGANIZATION The course is aimed at designing the different computer components (circuits) and connecting these components in a way to achieve the goals of a specific architectures. Computer (hardware) consists of processor, memory and I/O units. Processor itself consists of Arithmetic Logic Unit (ALU) and Control unit. All the above units are designed using primitive logic circuits.

COURSE OBJECTIVES Understanding the basic Laws of Boolean algebra. Designing and using the basic logic devices. Understanding the operation of the main computer units and their design. Interconnecting the various computer units to achieve the specific architecture. Presenting the attributes of the different architectures. Programming specific architecture using its instruction set (machine instruction). Explaining the Interaction between Computer hardware and the operating system.

COURSE OUTLINE The course will consist of two parts: The first part is Logic design: in which the primitive components, by which the different devices are designed, are presented. The second part is intended for interconnecting the components presented in first part in a way to build a logical system (computer organization).

PART 1: LOGIC DESIGN Introduction to number systems and arithmetic operations in binary system. Combinational circuits: Logic Gates (AND, OR, NOT, NOR, NAND and XOR), in this regards we will give the truth tables and symbols for each. Laws of Boolean algebra, deriving logical expression and simplification. Karnaugh maps and its use for simplification. half and full adders and binary coded decimal adders

PART 1: LOGIC DESIGN devices include: Decoder. Encoder. Multiplexers/ De-multiplexer. Comparator. Sequential circuits include : Flip/Flops and counter Design Mealy and MOORE machines.

PART 2: COMPUTER ORGANIZATION chapter 3: computer system chapter 7: Input/output chapter 8: Operating System Support. chapter 9: Computer Arithmetic chapter 10: Instruction Sets. chapter 11: : Instruction Sets: Addressing Modes and Format. chapter 12: CPU structure chapter 16 : Control Unit chapter 17: Micro Programmed Control Unit.

NUMBERS AND BOOLEAN ALGEBRA Author: Abhinav Bhatele Revised By: Dr. M. Khamis FAll 2008

June 10 th, 2008 NUMBER SYSTEMS To get started, we’ll discuss one of the fundamental concepts underlying digital computer design: Number Systems and Boolean Algebra Deep down inside, computers work with just 1 s and 0 s. Computers use voltages to represent information. In modern CPUs the voltage is usually limited to 1. 6 -1. 8 V to minimize power consumption. It’s convenient for us to translate these analog 1 voltages into the discrete, or digital, values 1 and 0. But how can binary system be useful for anything? First, we’ll see how to represent numbers with just 1 s and 0 s. Then we’ll introduce special operations for computing with 1 s and 0 s, by treating them as the logical values “true” and “false. ” 0 Volts 1. 8 0 8

June 10 th, 2008 TODAY’S LECTURE Number systems Review of binary number representation Number Systems and Boolean Algebra How to convert between binary and decimal representations Octal and Hex representations Basic boolean operations AND, OR and NOT The idea of “Truth Table” Boolean functions and expressions Truth table for Boolean expressions 9

Numbers consist of a bunch of digits, each with a weight These weights are all powers of the base, which is 10. We can rewrite this: To find the decimal value of a number, multiply each digit by its weight and sum the products. Number Systems and Boolean Algebra June 10 th, 2008 DECIMAL REVIEW (1 x 102) + (6 x 101) + (2 x 100) + (3 x 10 -1) + (7 x 10 -2) + (5 x 10 -3) = 162. 375 10

We can use the same trick to convert binary, or base 2, numbers to decimal. This time, the weights are powers of 2. Example: 1101. 01 in binary The decimal value is: (1 x 23) + (1 x 22) + (0 x 21) + (1 x 20) + (0 x 2 -1) + (1 x 2 -2) = 8 + 4 + 0 + 1 + 0. 25 = 13. 25 Number Systems and Boolean Algebra June 10 th, 2008 CONVERTING BINARY TO DECIMAL 11

162 / 2 81 / 2 40 / 2 20 / 2 10 / 2 5/2 2/2 1/2 = 81 = 40 = 20 = 10 =5 =2 =1 =0 rem 1 rem 0 rem 1 So, 162. 37510 = 10100010. 0112 0. 375 x 2 = 0. 750 x 2 = 1. 500 0. 500 x 2 = 1. 000 Number Systems and Boolean Algebra To convert a decimal integer into binary, keep dividing by 2 until the quotient is 0. Collect the remainders in reverse order. To convert a fraction, keep multiplying the fractional part by 2 until it becomes 0. Collect the integer parts in forward order. Example: 162. 375: June 10 th, 2008 CONVERTING DECIMAL TO BINARY 12

This works for converting from decimal to any base Why? Think about converting 162. 375 from decimal to decimal. 162 / 10 = 16 16 / 10 = 1 1 / 10 = 0 rem 2 rem 6 rem 1 Each division strips off the rightmost digit (the remainder). The quotient represents the remaining digits in the number. Similarly, to convert fractions, each multiplication strips off the leftmost digit (the integer part). The fraction represents the remaining digits. 0. 375 x 10 = 3. 750 0. 750 x 10 = 7. 500 0. 500 x 10 = 5. 000 Number Systems and Boolean Algebra June 10 th, 2008 WHY DOES THIS WORK? 13

The hexadecimal system uses 16 digits: 0123456789 ABCDEF You can convert between base 10 and base 16 using techniques like the ones we just showed for converting between decimal and binary. For our purposes, base 16 is most useful as a “shorthand” notation for binary numbers. Since 16 = 24, one hexadecimal digit is equivalent to 4 binary digits. It’s often easier to work with a number like B 4 instead of 10110100. Hex is frequently used to specify things like 32 -bit IP addresses and 24 -bit colors. Number Systems and Boolean Algebra June 10 th, 2008 BASE 16 IS USEFUL TOO 14

Converting from hexadecimal to binary is easy: just replace each hex digit with its equivalent 4 -bit binary sequence. 261. 3516 = 2 6 1. 3 516 = 0010 0110 0001. 0011 01012 To convert from binary to hex, make groups of 4 bits, starting from the binary point. Add 0 s to the ends of the number if needed. Then, just convert each bit group to its corresponding hex digit. 10110100. 0010112 = 1011 0100 = B 4 . 0010. 2 11002 C 16 Hex Binary 0 0000 4 0100 8 1000 C 1100 1 0001 5 0101 9 1001 D 1101 2 0010 6 0110 A 1010 E 1110 3 0011 7 0111 B 1011 F 1111 Number Systems and Boolean Algebra June 10 th, 2008 BINARY AND HEXADECIMAL CONVERSIONS 15

2’S COMPLEMENT Binary number can be represented using sign and magnitude. If N bits are used to represent the number, then the last bit is used to hold the sign of the number while the other (N-1) bits are used to represent the value. 0 is used for –ve sign and 1 is used for +ve sign. To get the 2’s complement for any number follow the following two steps: Convert each bit in the value into its complement (1 to 0 and vice versa) 2. Add 1 to the result of step 1. 1.

BINARY ADDITION & SUBTRACTION If the number is +ve keep it in sign and magnitude form, otherwise represent the number (magnitude only) using its 2’s complement. Add the binary numbers in the ordinary way as the decimal numbers. The addition in decimal makes carry 1 for the next digit for each 10 collected in the sum, and the reset which will be less than 10 is left as result of the addition of corresponding bits. This operation continues until adding all of the corresponding bits in the numbers.

BINARY ADDITION & SUBTRACTION C( ONTINUED) The addition in binary is exactly the same as decimal with only one difference, which is, carry 1 is taken for the next digit for each 2 collected in the sum, and the reset which is less than 2 is left as result of the addition of corresponding bits. The addition is continued for all bits including the sign bit, and in order to get correct answer the number must be represented in enough number of bits. Any carry after the sign bit is discarded. The value of the negative result is represented in the 2’s complement (i. e. the actual value is the 2’s complement of the result once again).

Computers are binary devices. We’re forced to think in terms of base 2. Today we learned how to convert numbers between binary, decimal and hexadecimal. Also, we have seen: We use 0 and 1 as abstractions for analog voltages. We showed how to represent numbers using just these two signals. Next we’ll introduce special operations for binary values and show those correspond to circuits. Number Systems and Boolean Algebra June 10 th, 2008 NUMBER SYSTEMS SUMMARY 19

How logical functions can be defined for expressing computations How to build circuits that implement our functions in hardware Number Systems and Boolean Algebra So far, we’ve talked about how arbitrary numbers can be represented using just the two binary values 1 and 0. Now we’ll interpret voltages as the logical values “true” and “false” instead. We’ll show: June 10 th, 2008 BOOLEAN OPERATIONS 20

Earlier, we used electrical voltages to represent two discrete values 1 and 0, from which binary numbers can be formed. It’s also possible to think of voltages as representing two logical values, true and false. For simplicity, we often still write digits instead: True June 10 th, 2008 BOOLEAN VALUES Number Systems and Boolean Algebra is true 0 is false Volts 1. 8 1 False We will use this interpretation along with special operations to design functions and hardware for doing arbitrary computations. 0 21

Computers take inputs and produce outputs, just like functions in math! A function table is unique but infinite Logical functions can be expressed in two ways: Number Systems and Boolean Algebra An expression is finite but not unique f(x, y) = 2 x + y =x+x+y = 2(x + y/2) =. . . June 10 th, 2008 FUNCTIONS A finite, but non-unique Boolean expression. A truth table, which will turn out to be unique and finite. 22

June 10 th, 2008 BASIC BOOLEAN OPERATIONS There are three basic operations for logical values. AND (product) of two inputs Expression: xy, or x y Truth table: OR (sum) of two inputs x+y NOT (complement) on one input x’ Number Systems and Boolean Algebra Operation: 23

We can use these basic operations to form more complex expressions: f(x, y, z) = (x + y’)z + x’ Some terminology and notation: f is the name of the function. (x, y, z) are the input variables, each representing 1 or 0. Listing the inputs is optional, but sometimes helpful. A literal is any occurrence of an input variable or its complement. The function above has four literals: x, y’, z, and x’. Precedences are important, but not too difficult. NOT has the highest precedence, followed by AND, and then OR. Fully parenthesized, the function above would be kind of messy: Number Systems and Boolean Algebra June 10 th, 2008 BOOLEAN EXPRESSIONS f(x, y, z) = (((x +(y’))z) + x’) 24

A truth table shows all possible inputs and outputs of a function. Remember that each input variable represents either 1 or 0. Because there are only a finite number of values (1 and 0), truth tables themselves are finite. n A function with n variables has 2 possible combinations of inputs. Inputs are listed in binary order—in this example, from 000 to 111. f(x, y, z) = (x + y’)z + x’ f(0, 0, 0) f(0, 0, 1) f(0, 1, 0) f(0, 1, 1) f(1, 0, 0) f(1, 0, 1) f(1, 1, 0) f(1, 1, 1) = (0 + 1)0 + 1 = (0 + 1)1 + 1 = (0 + 0)0 + 1 = (0 + 0)1 + 1 = (1 + 1)0 + 0 = (1 + 1)1 + 0 = (1 + 0)0 + 0 = (1 + 0)1 + 0 =1 =1 =0 =1 Number Systems and Boolean Algebra June 10 th, 2008 TRUTH TABLES 25

June 10 th, 2008 PRIMITIVE LOGIC GATES Each of our basic operations can be implemented in hardware using a primitive logic gate. These gates output the product, sum or complement of their inputs. Operation: AND (product) of two inputs Expression: xy, or x y Logic gate: OR (sum) of two inputs x+y NOT (complement) on one input x’ Number Systems and Boolean Algebra Symbols for each of the logic gates are shown below. 26

(x + y’)z + x’ Number Systems and Boolean Algebra Any Boolean expression can be converted into a circuit by combining basic gates in a relatively straightforward way. The diagram below shows the inputs and outputs of each gate. The precedences are explicit in a circuit. Clearly, we have to make sure that the hardware does operations in the right order! June 10 th, 2008 EXPRESSIONS AND CIRCUITS 27

After finding the circuit inputs and outputs, you can come up with either an expression or a truth table to describe what the circuit does. You can easily convert between expressions and truth tables. Find the circuit’s inputs and outputs Find a Boolean expression for the circuit Number Systems and Boolean Algebra June 10 th, 2008 CIRCUIT ANALYSIS SUMMARY Find a truth table for the circuit 28

We can interpret high or low voltage as representing true or false. A variable whose value can be either 1 or 0 is called a Boolean variable. AND, OR, and NOT are the basic Boolean operations. We can express Boolean functions with either an expression or a truth table. Every Boolean expression can be converted to a circuit. Next, we’ll look at how Boolean algebra can help simplify expressions, which in turn will lead to simpler circuits. Number Systems and Boolean Algebra June 10 th, 2008 BOOLEAN OPERATIONS SUMMARY 29

Last time we talked about Boolean functions, Boolean expressions, and truth tables. Now we’ll learn how to how use Boolean algebra to simplify Booleans expressions. Last time, we saw this expression and converted it to a circuit: (x + y’)z + x’ Can we make this circuit “better”? • Cheaper: fewer gates • Faster: fewer delays from inputs to outputs Number Systems and Boolean Algebra June 10 th, 2008 BOOLEAN ALGEBRA 30

Normal mathematical expressions can be simplified using the laws of algebra For binary systems, we can use Boolean algebra, which is superficially similar to regular algebra There are many differences, due to having only two values (0 and 1) to work with having a complement operation the OR operation is not the same as addition Number Systems and Boolean Algebra June 10 th, 2008 EXPRESSION SIMPLIFICATION 31

Number Systems and Boolean Algebra A Boolean algebra requires A set of elements B, which needs at least two elements (0 and 1) Two binary (two-argument) operations OR and AND A unary (one-argument) operation NOT The axioms below must always be true (textbook, p. 42) The magenta axioms deal with the complement operation Blue axioms (especially 15) are different from regular algebra June 10 th, 2008 FORMAL DEFINITION OF BOOLEAN ALGEBRA 32

The associative laws show that there is no ambiguity about a term such as x + y + z or xyz, so we can introduce multiple-input primitive gates: The left and right columns of axioms are duals exchange all ANDs with ORs, and 0 s with 1 s The dual of any equation is always true Number Systems and Boolean Algebra June 10 th, 2008 COMMENTS ON THE AXIOMS 33

We can show that these axioms are valid, given the definitions of AND, OR and NOT The first 11 axioms are easy to see from these truth tables alone. For example, x + x’ = 1 because of the middle two lines below (where y = x’) Number Systems and Boolean Algebra June 10 th, 2008 ARE THESE AXIOMS FOR REAL? 34

We can make up truth tables to prove (both parts of) De. Morgan’s law For (x + y)’ = x’y’, we can make truth tables for (x + y)’ and for x’y’ In each table, the columns on the left (x and y) are the inputs. The columns on the right are outputs. In this case, we only care about the columns in blue. The other “outputs” are just to help us find the blue columns. Since both of the columns in blue are the same, this shows that (x + y)’ and x’y’ are equivalent Number Systems and Boolean Algebra June 10 th, 2008 PROVING THE REST OF THE AXIOMS 35

We can now start doing some simplifications [ Distributive; x’y’ + x’y = x’(y’ + y) ] [ Axiom 7; y’ + y = 1 ] [ Axiom 2; x’ 1 = x’ ] [ Distributive ] [ Axiom 7; x’ + x = 1 ] [ Axiom 2 ] Number Systems and Boolean Algebra x’y’ + xyz + x’y = x’(y’ + y) + xyz = x’ 1 + xyz = x’ + xyz = (x’ + x)(x’ + yz) = 1 (x’ + yz) = x’ + yz June 10 th, 2008 SIMPLIFICATION WITH AXIOMS 36

Here are two different but equivalent circuits. In general the one with fewer gates is “better”: It costs less to build It requires less power But we had to do some work to find the second form Number Systems and Boolean Algebra June 10 th, 2008 LET’S COMPARE THE RESULTING CIRCUITS 37

Here are some more useful laws. Notice the duals again! We can prove these laws by either Making truth tables: Using the axioms: x + x’y = (x + x’)(x + y) = 1 (x + y) =x+y Number Systems and Boolean Algebra June 10 th, 2008 SOME MORE LAWS [ Distributive ] [ x + x’ = 1 ] [ Axiom 3 ] 38

The complement of a function always outputs 0 where the original function outputted 1, and 1 where the original produced 0. In a truth table, we can just exchange 0 s and 1 s in the output column(s) f(x, y, z) = x(y’z’ + yz) Number Systems and Boolean Algebra June 10 th, 2008 THE COMPLEMENT OF A FUNCTION 39

f(x, y, z) = x(y’z’ + yz) f’(x, y, z) = ( x(y’z’ + yz) )’ = x’ + (y’z’ + yz)’ = x’ + (y’z’)’ (yz)’ = x’ + (y + z)(y’ + z’) [ complement both sides ] [ because (xy)’ = x’ + y’ ] [ because (x + y)’ = x’ y’ ] [ because (xy)’ = x’ + y’, twice] You can also take the dual of the function, and then complement each literal If f(x, y, z) = x(y’z’ + yz)… … the dual of f is x + (y’ + z’)(y + z)… … then complementing each literal gives x’ + (y + z)(y’ + z’)… … so f’(x, y, z) = x’ + (y + z)(y’ + z’) Number Systems and Boolean Algebra You can use De. Morgan’s law to keep “pushing” the complements inwards June 10 th, 2008 COMPLEMENTING A FUNCTION ALGEBRAICALLY 40

So far: A bunch of Boolean algebra trickery for simplifying expressions and circuits The algebra guarantees us that the simplified circuit is equivalent to the original one Next: Introducing some standard forms and terminology An alternative simplification method We’ll start using all this stuff to build analyze bigger, more useful, circuits Number Systems and Boolean Algebra June 10 th, 2008 SUMMARY SO FAR 41

PARITY CHECKING Parity checking is used to check the correctness or erroneous of data. Circuit used to raise 1 on its output when its input data contain even number of 1’s is called even parity circuit, otherwise it called odd parity circuit. Parity checking is used with memory to ensure the read data is exactly as written one or otherwise, it interrupts the main processor. Also, it is used within the modem to ensure the correct arrival of the received data.

PARITY CHECKING WITH THE MAIN MEMORY Parity RAM Data RAM Parity cct To interrut processor Parity cct

HOW IS PARITY CIRCUITS DETECT THE ERROR? Original Correct defected Data circuit Odd odd even Even odd even The table depicts the expected output of the parity checking during reading data (yellow circuit). Note that the output will be always 1 when memory is defected, otherwise, it will be 0.

DESIGN PARITY CHECKING FOR 3 -INPUTS For sake of simplicity 3 -inputs are considered. The truth table will be as shown. The output (F) of the even parity circuit is 1 when the number of the 1’s in the inputs are even. F= xyz’ + xy’z + x’y’z’ (Draw the corresponding circuit for the above logic expression to get the odd parity circuit for 3 -inputs) x y z F 1 1 1 0 1 1 1 0 0 0 0 1

HOW TO ADD BINARY NUMBERS Consider adding two 1 -bit binary numbers x and y 0+0 = 0 0+1 = 1 1+0 = 1 1+1 = 10 x y Carry Sum 0 0 0 1 1 0 Carry is x AND y Sum is x XOR y The circuit to compute this is called a half-adder

THE HALF-ADDER Sum = x XOR y Carry = x AND y

USING HALF ADDERS We can then use a half-adder to compute the sum of two Boolean numbers 1 0 0 1 1 0 0 +1 1 1 0 ? 0 1 0

HOW TO FIX THIS We need to create an adder that can take a carry bit as an additional input Inputs: x, y, carry in Outputs: sum, carry out x y c carry sum 1 1 1 1 0 1 0 1 1 0 What about the carry out? 1 0 0 0 1 It’s 1 if either (or both): x+y = 10 x+y = 01 and carry in = 1 0 1 1 1 0 0 1 0 0 0 This is called a full adder Will add x and y with a half-adder Will add the sum of that to the carry in

THE FULL ADDER The “HA” boxes are half-adders c X Y x y X Y HA HA S s C S C c

THE FULL ADDER c The full circuitry of the full adder s x y c

ADDING BIGGER BINARY NUMBERS (4 BITS PARALLEL BINARY ADDER) This design is available with IC 7483

SEVEN SEGMENT Example Seven-segment display used to display binary values visually To do so it needs a driver to convert from 4 bit binary to 7 segments output.

D’ OUTPUT OF THE DRIVER (DECODER TO 7 SEGMENT)

SIMPLIFIED EXPRESSION OF “D” KARNAUGH MAP METHOD Don’t cares simplify the expression a lot

USING DECODER TO 7 -SEGMENT TO DISPLAY THE OUTPUT OF THE 4 -BITS ADDER ON 7 -SEGMENT All output of the decoder to 7 -segments is calculated in similar way (IC 7447 performing the function of the decoder to 7 -segments).

ADDING BIGGER BINARY NUMBERS A half adder has 4 logic gates A full adder has two half adders plus a OR gate To add n bit binary numbers, you need 1 HA and n-1 FAs To add 32 bit binary numbers, you need 1 HA and 31 FAs Total of 9 logic gates Total of 4+9*31 = 283 logic gates To add 64 bit binary numbers, you need 1 HA and 63 FAs Total of 4+9*63 = 571 logic gates

MORE ABOUT LOGIC GATES To implement a logic gate in hardware, you use a transistor Transistors are all enclosed in an “IC”, or integrated circuit The current Intel Pentium IV processors have 55 million transistors!

SUMMARY: DIGITAL LOGIC BASICS Hardware consists of a few simple building blocks These are called logic gates AND, OR, NOT, … NAND, NOR, XOR, … Logic gates are built using transistors NOT gate can be implemented by a single transistor AND gate requires 3 transistors Transistors are the fundamental devices Pentium consists of 3 million transistors Compaq Alpha consists of 9 million transistors Now we can build chips with more than 100

BASIC CONCEPTS Simple gates AND OR NOT Functionality can be expressed by a truth table A truth table lists output for each possible input combination Precedence NOT > AND > OR F=AB+AB = (A (B)) + ((A) B)

BASIC CONCEPTS (CONT. ) Additional useful gates NAND NOR XOR NAND = AND + NOT NOR = OR + NOT XOR implements exclusive. OR function NAND and NOR gates require only 2 transistors AND and OR need 3 transistors!

BASIC CONCEPTS (CONT. ) Basic building block: Transistor Three connection points Base Emitter Collector Transistor can operate Linear mode Used in amplifiers Switching mode Used to implement digital circuits

BASIC CONCEPTS (CONT. ) Number of functions With N logical variables, we can define N 22 functions Some of them are useful AND, NOR, XOR, … Some are not useful: Output is always 1 Output is always 0 “Number of functions” definition is useful in proving completeness property

BASIC CONCEPTS (CONT. ) Complete sets A set of gates is complete If we can implement any logical function using only the type of gates in the set You can uses as many gates as you want Some example complete sets {AND, OR, NOT} complete set {AND, NOT} {OR, NOT} {NAND} {NOR} Minimal Not a minimal complete set A complete set with no redundant elements.

BASIC CONCEPTS (CONT. ) Proving NAND gate is universal NAND gate is called universal gate

BASIC CONCEPTS (CONT. ) Proving NOR gate is universal NOR gate is called universal gate

LOGIC CHIPS

LOGIC CHIPS (CONT. ) Integration levels SSI (small scale integration) Introduced in late 1960 s 1 -10 gates (previous examples) MSI (medium scale integration) Introduced in late 1960 s 10 -100 gates LSI (large scale integration) Introduced in early 1970 s 100 -10, 000 gates VLSI (very large scale integration) Introduced in late 1970 s More than 10, 000 gates

LOGIC FUNCTIONS Logical functions can be expressed in several ways: Truth table Logical expressions Graphical form Example: Majority function Output is 1 whenever majority of inputs is 1 We use 3 -input majority function

LOGIC FUNCTIONS (CONT. ) 3 -input majority function A B C F 0 0 1 1 0 1 0 1 0 0 0 1 1 1 Logical expression form F=AB+BC+AC

LOGICAL EQUIVALENCE All three circuits implement F = A B function

LOGICAL EQUIVALENCE (CONT. ) Proving logical equivalence of two circuits Derive the logical expression for the output of each circuit Show that these two expressions are equivalent Two ways: You can use the truth table method For every combination of inputs, if both expressions yield the same output, they are equivalent Good for logical expressions with small number of variables You can also use algebraic manipulation Need Boolean identities

LOGICAL EQUIVALENCE (CONT. ) Derivation of logical expression from a circuit Trace from the input to output Write down intermediate logical expressions along the path

LOGICAL EQUIVALENCE (CONT. ) Proving logical equivalence: Truth table method A 0 0 1 1 B 0 1 F 1 = A B F 3 = (A + B) 0 0 0 1 1

LOGIC CIRCUIT DESIGN PROCESS A simple logic design process involves Problem specification Truth table derivation Derivation of logical expression Simplification of logical expression Implementation

DERIVING LOGICAL EXPRESSIONS Derivation of logical expressions from truth tables sum-of-products (SOP) form product-of-sums (POS) form SOP form Write an AND term for each input combination that produces a 1 output Write the variable if its value is 1; complement otherwise OR the AND terms to get the final expression POS form Dual of the SOP form

DERIVING LOGICAL EXPRESSIONS (CONT. ) A 3 -input majority function B C F 0 0 0 0 1 1 0 0 1 1 1 0 1 0 0 1 1 1 SOP logical expression Four product terms Because there are 4 rows with a 1 output F=ABC+ABC

DERIVING LOGICAL EXPRESSIONS (CONT. ) A 3 -input majority function B C F 0 0 0 0 1 1 0 0 1 1 1 0 1 0 0 1 1 1 POS logical expression Four sum terms Because there are 4 rows with a 0 output F = (A + B + C)

LOGICAL EXPRESSION SIMPLIFICATION Two basic methods Algebraic manipulation Use Boolean laws to simplify the expression Difficult to use Don’t know if you have the simplified form Karnaugh map (K-map) method Graphical method Easy to use Can be used to simplify logical expressions with a few variables

ALGEBRAIC MANIPULATION Majority function example Added extra ABC+ABC+ABC = ABC+ABC+ABC+ABC We can now simplify this expression as BC+AC+AB A difficult method to use for complex expressions

KARNAUGH MAP METHOD Note the order

KARNAUGH MAP METHOD (CONT. ) Simplification examples

KARNAUGH MAP METHOD (CONT. ) First and last columns/rows are adjacent

KARNAUGH MAP METHOD (CONT. ) Minimal expression depends on groupings

KARNAUGH MAP METHOD (CONT. ) No redundant groupings

KARNAUGH MAP METHOD (CONT. ) Example Seven-segment display Need to select the right LEDs to display a digit

KARNAUGH MAP METHOD (CONT. )

KARNAUGH MAP METHOD (CONT. ) Don’t cares simplify the expression a lot

IMPLEMENTATION USING NAND GATES Using NAND gates Get an equivalent expression AB+CD=AB+CD Using de Morgan’s law AB+CD=AB. CD Can be generalized Majority function A B + B C + AC = A B. BC. AC Idea: NAND Gates: Sum-of-Products, NOR Gates: Product-of-Sums

IMPLEMENTATION USING NAND GATES (CONT. ) Majority function

INTRODUCTION TO COMBINATIONAL CIRCUITS Combinational circuits Output depends only on the current inputs Combinational circuits provide a higher level of abstraction Help in reducing design complexity Reduce chip count We look at some useful combinational circuits

MULTIPLEXERS Multiplexer data inputs n selection inputs a single output 2 n Selection input determines the input that should be connected to the output 4 -data input MUX

MULTIPLEXERS (CONT. ) 4 -data input MUX implementation

MULTIPLEXERS (CONT. ) MUX implementations

MULTIPLEXERS (CONT. ) Example chip: 8 -to-1 MUX

MULTIPLEXERS (CONT. ) Efficient implementation: Majority function

DEMULTIPLEXERS (DEMUX) Demultiplexer a single input n selection inputs 2 n outputs

DECODERS Decoder selects one-out-of-N inputs

DECODERS (CONT. ) Logic function implementation

COMPARATOR Used to implement comparison operators (= , > , < , , )

A=B: Ox = Ix (x=A<B, A=B, & A>B) COMPARATOR (CONT. ) 4 -bit magnitude comparator chip

COMPARATOR (CONT. ) Serial construction of an 8 -bit comparator

1 -BIT COMPARATOR x>y CMP x=y x<y x x y y x>y x=y x<y

8 -BIT COMPARATOR xn>yn xn=yn x>y CMP xn<yn x=y x<y x y

ADDERS Half-adder Adds two bits Produces a sum and carry Problem: Cannot use it to build larger inputs Full-adder Adds three 1 -bit values Like half-adder, produces a sum and carry Allows building N-bit adders Simple technique Connect Cout of one adder to Cin of the next These are called ripple-carry adders

ADDERS (CONT. )

ADDERS (CONT. ) A 16 -bit ripple-carry adder

ADDERS (CONT. ) Ripple-carry adders can be slow Delay proportional to number of bits Carry lookahead adders Eliminate the delay of ripple-carry adders Carry-ins are generated independently C 0 = A 0 B 0 C 1 = A 0 B 0 A 1 + A 0 B 1 + A 1 B 1 . . . Requires complex circuits Usually, a combination carry lookahead and ripple-carry techniques are used

PROGRAMMABLE LOGIC ARRAYS PLAs Implement sum-of-product expressions No need to simplify the logical expressions Take N inputs and produce M outputs Each input represents a logical variable Each output represents a logical function output Internally uses An AND array Each AND gate receives 2 N inputs and their complements An OR array

PROGRAMMABLE LOGIC ARRAYS (CONT. ) A blank PLA with 2 inputs and 2 outputs

PROGRAMMABLE LOGIC ARRAYS (CONT. ) Implementation examples

PROGRAMMABLE LOGIC ARRAYS (CONT. ) Simplified notation

1 -BIT ARITHMETIC AND LOGIC UNIT Preliminary ALU design 2’s complement Required 1 is added via Cin

1 -BIT ARITHMETIC AND LOGIC UNIT (CONT. ) Final design

ARITHMETIC AND LOGIC UNIT (CONT. ) 16 -bit ALU

ARITHMETIC AND LOGIC UNIT (CONT’D) 4 -bit ALU

INTRODUCTION TO SEQUENTIAL CIRCUITS Output depends on current as well as past inputs Depends on the history Have “memory” property Sequential circuit consists of Combinational circuit Feedback circuit Past input is encoded into a set of state variables Uses feedback (to feed the state variables) Simple feedback Uses flip flops

INTRODUCTION (CONT. ) Main components of a sequential circuit

CLOCK SIGNAL

CLOCK SIGNAL (CONT. ) Clock serves two distinct purposes Synchronization point Start of a cycle End of a cycle Intermediate point at which the clock signal changes levels Timing information Clock period, ON, and OFF periods Propagation delay Time required for the output to react to changes in the inputs

CLOCK SIGNAL (CONT. )

LATCHES Can remember a bit Level-sensitive (not edge-sensitive) A NOR gate implementation of SR latch

LATCHES (CONT. ) SR latch outputs follow inputs In clocked SR latch, outputs respond at specific instances Uses a clock signal

LATCHES (CONT. ) D Latch Avoids the SR = 11 state

FLIP-FLOPS Edge-sensitive devices Changes occur either at positive or negative edges Positive edge-triggered D flip-flop

FLIP-FLOPS (CONT. ) Notation Not strictly followed in the literature We follow the following notation for latches and flip-flops Latches Low level High level Flip-flops Positive edge Negative edge

FLIP-FLOPS (CONT. )

EXAMPLE SEQUENTIAL CIRCUITS (CONT. ) 74164 shift Register chip

MEMORY DESIGN WITH D FLIP FLOPS Require separate data in and out lines