Computer Organization and Architecture Chapter 14 Control Unit

Computer Organization and Architecture Chapter 14 Control Unit Operation

Micro-Operations z A computer executes a program z Fetch/execute cycle z Each cycle has a number of steps ysee pipelining z Called micro-operations z Each step does very little z Atomic operation of CPU

Constituent Elements of Program Execution

Fetch - 4 Registers z Memory Address Register (MAR) y. Connected to address bus y. Specifies address for read or write op z Memory Buffer Register (MBR) y. Connected to data bus y. Holds data to write or last data read z Program Counter (PC) y. Holds address of next instruction to be fetched z Instruction Register (IR) y. Holds last instruction fetched

Fetch Sequence z Address of next instruction is in PC z Address (MAR) is placed on address bus z Control unit issues READ command z Result (data from memory) appears on data bus z Data from data bus copied into MBR z PC incremented by 1 (in parallel with data fetch from memory) z Data (instruction) moved from MBR to IR z MBR is now free for further data fetches

Fetch Sequence (symbolic) z t 1: MAR <- (PC) z t 2: MBR <- (memory) z PC <- (PC) +1 z t 3: IR <- (MBR) z (tx = time unit/clock cycle) z or z t 1: MAR <- (PC) z t 2: MBR <- (memory) z t 3: PC <- (PC) +1 z IR <- (MBR)

Rules for Clock Cycle Grouping z Proper sequence must be followed y. MAR <- (PC) must precede MBR <- (memory) z Conflicts must be avoided y. Must not read & write same register at same time y. MBR <- (memory) & IR <- (MBR) must not be in same cycle z Also: PC <- (PC) +1 involves addition y. Use ALU y. May need additional micro-operations

Indirect Cycle z MAR <- (IRaddress) - address field of IR z MBR <- (memory) z IRaddress <- (MBRaddress) z MBR contains an address z IR is now in same state as if direct addressing had been used z (What does this say about IR size? )

Interrupt Cycle z t 1: MBR <-(PC) z t 2: MAR <- save-address z PC <- routine-address z t 3: memory <- (MBR) z This is a minimum y. May be additional micro-ops to get addresses y. N. B. saving context is done by interrupt handler routine, not micro-ops

Execute Cycle (ADD) z Different for each instruction z e. g. ADD R 1, X - add the contents of location X to Register 1 , result in R 1 z t 1: MAR <- (IRaddress) z t 2: MBR <- (memory) z t 3: R 1 <- R 1 + (MBR) z Note no overlap of micro-operations

Execute Cycle (ISZ) z ISZ X - increment and skip if zero yt 1: yt 2: yt 3: yt 4: y MAR <- (IRaddress) MBR <- (memory) MBR <- (MBR) + 1 memory <- (MBR) if (MBR) == 0 then PC <- (PC) + 1 z Notes: yif is a single micro-operation y. Micro-operations done during t 4

Execute Cycle (BSA) z BSA X - Branch and save address y. Address of instruction following BSA is saved in X y. Execution continues from X+1 yt 1: MAR <- (IRaddress) y MBR <- (PC) yt 2: PC <- (IRaddress) y memory <- (MBR) yt 3: PC <- (PC) + 1

Functional Requirements z Define basic elements of processor z Describe micro-operations processor performs z Determine functions control unit must perform

Basic Elements of Processor z ALU z Registers z Internal data pahs z External data paths z Control Unit

Types of Micro-operation z Transfer data between registers z Transfer data from register to external z Transfer data from external to register z Perform arithmetic or logical ops

Functions of Control Unit z Sequencing y. Causing the CPU to step through a series of microoperations z Execution y. Causing the performance of each micro-op z This is done using Control Signals

Control Signals (1) z Clock y. One micro-instruction (or set of parallel microinstructions) per clock cycle z Instruction register y. Op-code for current instruction y. Determines which micro-instructions are performed

Control Signals (2) z Flags y. State of CPU y. Results of previous operations z From control bus y. Interrupts y. Acknowledgements

Control Signals - output z Within CPU y. Cause data movement y. Activate specific functions z Via control bus y. To memory y. To I/O modules

Example Control Signal Sequence - Fetch z MAR <- (PC) y. Control unit activates signal to open gates between PC and MAR z MBR <- (memory) y. Open gates between MAR and address bus y. Memory read control signal y. Open gates between data bus and MBR

Internal Organization z Usually a single internal bus z Gates control movement of data onto and off the bus z Control signals control data transfer to and from external systems bus z Temporary registers needed for properation of ALU

Hardwired Implementation (1) z Control unit inputs z Flags and control bus y. Each bit means something z Instruction register y. Op-code causes different control signals for each different instruction y. Unique logic for each op-code y. Decoder takes encoded input and produces single output yn binary inputs and 2 n outputs

Hardwired Implementation (2) z Clock y. Repetitive sequence of pulses y. Useful for measuring duration of micro-ops y. Must be long enough to allow signal propagation y. Different control signals at different times within instruction cycle y. Need a counter with different control signals for t 1, t 2 etc.

Problems With Hard Wired Designs z Complex sequencing & micro-operation logic z Difficult to design and test z Inflexible design z Difficult to add new instructions

Required Reading z Stallings chapter 14