Computer Organization and Architecture Chapter 12 Reduced Instruction

Computer Organization and Architecture Chapter 12 Reduced Instruction Set Computers 1

Major Advances in Computers(1) z The family concept y. IBM System/360 1964 y. DEC PDP-8 y. Separates architecture from implementation z Microporgrammed control unit y. Idea by Wilkes 1951 y. Produced by IBM S/360 1964 z Cache memory y. IBM S/360 model 85 1969 2

Major Advances in Computers(2) z Solid State RAM y(See memory notes) z Microprocessors y. Intel 4004 1971 z Pipelining y. Introduces parallelism into fetch execute cycle z Multiple processors 3

The Next Step - RISC z Reduced Instruction Set Computer z Key features y. Large number of general purpose registers yor use of compiler technology to optimize register use y. Limited and simple instruction set y. Emphasis on optimising the instruction pipeline 4

Comparison of processors z z CISC IBM 370/168 1973 z z No. of instruction 208 303 z z DEC VAX Intel 11/780 486 1978 1989 235 RISC Motorola MIPS 88000 R 4000 1988 1991 Superscalar IBM Intel RS/6000 80960 1990 1989 51 94 184 62 Instruction size (octets) 2 -6 2 -57 1 -11 4 32 4 4 or 8 z z Addressing modes 4 22 11 3 1 2 11 z z GP Registers 16 16 8 32 32 32 23 -256 z z Control memory (k bytes) (microprogramming) 420 480 246 0 0 5

Driving force for CISC z Software costs far exceed hardware costs z Increasingly complex high level languages z Semantic gap z Leads to: y. Large instruction sets y. More addressing modes y. Hardware implementations of HLL statements xe. g. CASE (switch) on VAX 6

Intention of CISC z Ease compiler writing z Improve execution efficiency y. Complex operations in microcode z Support more complex HLLs 7

Execution Characteristics z Operations performed z Operands used z Execution sequencing z Studies have been done based on programs written in HLLs z Dynamic studies are measured during the execution of the program 8

Operations z Assignments y. Movement of data z Conditional statements (IF, LOOP) y. Sequence control z Procedure call-return is very time consuming z Some HLL instruction lead to many machine code operations 9

Relative Dynamic Frequency Assign Loop Call If Go. To Other Dynamic Occurrence Pascal C 45 38 5 3 15 12 29 43 3 6 1 Machine Instruction (Weighted) Pascal C 13 13 42 32 31 33 11 21 3 1 Memory Reference (Weighted) Pascal C 14 15 33 26 44 45 7 13 2 1 10

Operands z Mainly local scalar variables z Optimisation should concentrate on accessing local variables Integer constant Scalar variable Array/structure Pascal 16 58 26 C 23 53 24 Average 20 55 25 11

Procedure Calls z Very time consuming z Depends on number of parameters passed z Depends on level of nesting z Most programs do not do a lot of calls followed by lots of returns z Most variables are local z (c. f. locality of reference) 12

Implications z Best support is given by optimising most used and most time consuming features z Large number of registers y. Operand referencing z Careful design of pipelines y. Branch prediction etc. z Simplified (reduced) instruction set 13

Large Register File z Software solution y. Require compiler to allocate registers y. Allocate based on most used variables in a given time y. Requires sophisticated program analysis z Hardware solution y. Have more registers y. Thus more variables will be in registers 14

Registers for Local Variables z Store local scalar variables in registers z Reduces memory access z Every procedure (function) call changes locality z Parameters must be passed z Results must be returned z Variables from calling programs must be restored 15

Register Windows z Only few parameters z Limited range of depth of call z Use multiple small sets of registers z Calls switch to a different set of registers z Returns switch back to a previously used set of registers 16

Register Windows cont. z Three areas within a register set y. Parameter registers y. Local registers y. Temporary registers from one set overlap parameter registers from the next y. This allows parameter passing without moving data 17

Overlapping Register Windows 18

Circular Buffer diagram 19

Operation of Circular Buffer z When a call is made, a current window pointer is moved to show the currently active register window z If all windows are in use, an interrupt is generated and the oldest window (the one furthest back in the call nesting) is saved to memory z A saved window pointer indicates where the next saved windows should restore to 20

Global Variables z Allocated by the compiler to memory y. Inefficient for frequently accessed variables z Have a set of registers for global variables 21

Registers v Cache z Large Register File Cache All local scalars Individual variables Compiler assigned global variables Save/restore based on procedure nesting z Register addressing Recently used local scalars Blocks of memory Recently used global variables Save/restore based on caching algorithm Memory addressing z z 22

Referencing a Scalar Window Based Register File 23

Referencing a Scalar - Cache 24

Compiler Based Register Optimization z Assume small number of registers (16 -32) z Optimizing use is up to compiler z HLL programs have no explicit references to registers y usually - think about C - register int z Assign symbolic or virtual register to each candidate variable z Map (unlimited) symbolic registers to real registers z Symbolic registers that do not overlap can share real registers z If you run out of real registers some variables use memory 25

Graph Coloring z Given a graph of nodes and edges z Assign a color to each node z Adjacent nodes have different colors z Use minimum number of colors z Nodes are symbolic registers z Two registers that are live in the same program fragment are joined by an edge z Try to color the graph with n colors, where n is the number of real registers z Nodes that can not be colored are placed in memory 26

Graph Coloring Approach 27

Why CISC (1)? z Compiler simplification? y. Disputed… y. Complex machine instructions harder to exploit y. Optimization more difficult z Smaller programs? y. Program takes up less memory but… y. Memory is now cheap y. May not occupy less bits, just look shorter in symbolic form x. More instructions require longer op-codes x. Register references require fewer bits 28

Why CISC (2)? z Faster programs? y. Bias towards use of simpler instructions y. More complex control unit y. Microprogram control store larger ythus simple instructions take longer to execute z It is far from clear that CISC is the appropriate solution 29

RISC Characteristics z One instruction per cycle z Register to register operations z Few, simple addressing modes z Few, simple instruction formats z Hardwired design (no microcode) z Fixed instruction format z More compile time/effort 30

RISC v CISC z Not clear cut z Many designs borrow from both philosophies z e. g. Power. PC and Pentium II 31

RISC Pipelining z Most instructions are register to register z Two phases of execution y. I: Instruction fetch y. E: Execute x. ALU operation with register input and output z For load and store y. I: Instruction fetch y. E: Execute x. Calculate memory address y. D: Memory x. Register to memory or memory to register operation 32

Effects of Pipelining 33

Optimization of Pipelining z Delayed branch y. Does not take effect until after execution of following instruction y. This following instruction is the delay slot 34

Normal and Delayed Branch Address 100 101 102 103 104 105 106 Normal LOAD X, A ADD 1, A JUMP 105 ADD A, B SUB C, B STORE A, Z Delayed LOAD X, A ADD 1, A JUMP 105 NOOP ADD A, B SUB C, B STORE A, Z Optimized LOAD X, A JUMP 105 ADD 1, A ADD A, B SUB C, B STORE A, Z 35

Use of Delayed Branch 36

Controversy z Quantitative y compare program sizes and execution speeds z Qualitative y examine issues of high level language support and use of VLSI real estate z Problems y No pair of RISC and CISC that are directly comparable y No definitive set of test programs y Difficult to separate hardware effects from complier effects y Most comparisons done on “toy” rather than production machines y Most commercial devices are a mixture 37

Required Reading z Stallings chapter 12 z Manufacturer web sites 38

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