Computer Organization 1 n IO Input Output Memory

Computer Organization 講師：陳育良 1

計算機功能單元 n I/O ¨ Input ¨ Output Memory n CPU n ¨ ALU ¨ Control Unit 4

計算機處理的資訊 Instruction(machine instructions, c. f. statements) n Program n ¨ Serial n of instructions Source program compiler Object Linkage Editor (reference to library) Image (executable) Loader Execution 5

資料編碼 Bit -> byte -> word n BCD(binary-coded decimal) n ¨ Mainframe n ASCII(American Standard Code for Information Interchage) ¨ 7 n bits EBCDIC(Extended Binary-Coded Decimal Interchange Code) ¨ 8 bits 6

ASCII Table vs. EBCDIC Table n ASCII Table vs EBCDIC Table 7

Functional Units n Input ¨ Keyboard, n mouse, joystick Memory ¨ Primary memory (DRAM、SDRAMSynchronous DRAM ) n Address (byte) ¨ Cache(SRAM-static ¨ Secondary n random access memory ) memory Disk、Tape、CD-ROM 8

CPU ALU(arithmetic and logic unit) n Registers (flip-flop)> Cache n ¨ high-speed n storage area within the CPU CU (control unit) ¨ Instruction Decoder and control logic ¨ Coordinator of other functional units ¨ Sending control signals n Timng signal 9

Instruction example Add Loca, R 0 n Prefer n ¨ Load Local, R 1 ¨ Add R 1, R 0 10

Registers n n n IR (Instruction register) PC (program counter) General-purpose register ¨ ¨ n AX, BX, DX, CX(8086) EAX, EBX, EDX, ECX(80 x 86) MAR(memory address register) Is the register of a computer's control unit that contains the address of a register to fetch or store from or to the computer storage. ¨ The memory address register is half of a minimal interface between a microprogram and computer storage. The other half is a memory data register. ¨ n MDR(memory data register) Is the register of a computer's control unit that contains the contents of a register to fetch or store from or to the computer storage. ¨ The memory data register is half of a minimal interface between a microprogram and computer storage. The other half is a memory address register ¨ 11

Load Instruction (load Loca, R 1) MAR <- PC; PC <- PC + 4; MDR <- MEM[MAR]; IR <- MDR; MAR <- Ra + ADJ 6(IR[5: 0]); (compute operand’s effective address) MDR <- MEM[MAR]; (get operand) Rdest <- MDR; (write register) 12

Store Instruction (store Local, R 1) MAR <- PC; PC <- PC + 4; MDR <- MEM[MAR]; IR <- MDR; MAR <- Ra + ADJ 6(IR[5: 0]); (compute operand’s effective address) MDR <- Rdest; (write MDR) MEM[MAR] <- MDR; (write memory) 13

Basic Computer Organization Revisited Memory I/O Data Processor General. Purpose Registers Control Logic MAR ALUs MDR Program PC 14

Interrupt Preempt vs non-preempt n Hardware interrupt n ¨ I/O n interrupt Softwre interrupt ¨ System calls Interrupt-service routine n Context Switching n ¨ Keep status of CPU in stack 15

BUS n n Connect various devices Addressing lines Control lines Single bus ¨ Low cost ¨ Two devices talk at any time n Multiple bus ¨ High cost ¨ Allow concurrency, high efficiency 16

Buffer register Equipped in devices for compensating the speed differences n Multiprogramming n ¨ CPU switches between running programs when they are blocked in I/O 17

System softwre I Coordinate the activities within computer system n Compiler n ¨ High level language n Do not need to know the underlay CPU n Assembler ¨ Assembly language n Need to know the architecture of CPU n Text editor 18

System softwre II n OS (Operating System) ¨ Distribute and manage resources for application programs ¨ Monolithic n Eg. Linux (but has been improved with loadable modules facility, also called kernel extension ) ¨ Microkernel n Eg. Windows NT 19

OS characteristics Multiprogramming n Multi-user vs. single user n Multitasking vs. single task n Time sharing n Preempted n ¨ Windows n NT, Linux Non-preempted ¨ Windows 3. 1 20

Performance n Hardware ¨ cpu, memory hierarchy, pipelining, ¨ dynamic scheduling (fetch-issue out of order), ¨ Speculation (fetch-issue-execute) Instruction set (CISC, RISC) n Compiler (optimization, instructions unrolling) n Processor time n ¨ Program + OS primitives 21

Memory hierarchy Cache principle n L 1 cache also called primary cache built into the CPU n L 2 cache also called secondary cache, usually resides on a separate chip from CPU n Program characteristic n ¨ Temporal locality ¨ Spatial locality 22

clock Clock cycle (R) n Period (P) n R=1/P n Hz(Hertz) n ¨ Cycles per second(每秒震動的次數) 500 MHz = 2 ns clock n 1. 25 GHz = 0. 8 ns clock n 23

Basic performance equation n T = (N x S) / R ¨ T: program execution time ¨ N: Total number of Ins been executed (not equal to ins of object code for looping visiting) ¨ S: Instruction stages ¨ R: Clock rate n n or no T -> down implies N, S down or R up Due to the variety of S, 900 MHz maybe run slow than 700 MHz 24

Pipeline and superscalar n Pipeline ¨ Overlapping the execution of instructions ¨ Eg. Multiple workers in an assembly line of factory n Superscalar ¨ Issue and execute multiple instructions at the same time with mutilple pipelines ¨ Concurrent execution (must be the same with the results of sequential execution) ¨ Eg. Multiple assembly lines 25

Instruction Set n CISC ¨ Complex Instruction Set Computer ¨ Eg. Intel CPU n RISC ¨ Reduced Instruction Set Computer ¨ Sun SPARC, Power PC, Alpha 26

Benchmark program n n n A baseline program for performance evaluation Real applications of various domains selected from SPEC (Standard Performance Evaluation Corporation) SPEC 95 – reference machine is SUN SPARC station 10/40 SPEC 2000 -300 MHz Ultra. SPARC-Iii SUN SPARC 10 SPEC evaluation= exe time of reference/exe time of target 27

Multiprocessor n Shared-memory multiprocessor ¨ Multiple n CPU share common memory Message-passing multicomputer ¨ Distributed computer architecuture ¨ Every processor has local memory and communicates with each other via LAN 28

History(Stored program computer) by John Von Neumann n First generation – 1945~1955 Vacuum tube ¨ millisecond ¨ n Second generation – 1955~1965 Transistor ¨ microsecond ¨ n Third generation – 1965 -1975 IC ¨ Microprogramming, pipeline, parallel, cache, virtual memory ¨ n Fourth generation – 1975 ~ VLSI (very large scale integration) ¨ Nanosecond ¨ 29