Computer Arithmetic 1 COMPUTER ARITHMETIC Arithmetic with Signed2s

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Computer Arithmetic 1 COMPUTER ARITHMETIC • Arithmetic with Signed-2's Complement Numbers • Multiplication and

Computer Arithmetic 1 COMPUTER ARITHMETIC • Arithmetic with Signed-2's Complement Numbers • Multiplication and Division • Floating-Point Arithmetic Operations • Decimal Arithmetic Unit • Decimal Arithmetic Operations Computer Organization Prof. H. Yoon

Computer Arithmetic 2 Addition and Subtraction SIGNED MAGNITUDEADDITION AND SUBTRACTION Addition: A + B

Computer Arithmetic 2 Addition and Subtraction SIGNED MAGNITUDEADDITION AND SUBTRACTION Addition: A + B ; A: Augend; B: Addend Subtraction: A - B: A: Minuend; B: Subtrahend Operation (+A) + (+B) (+A) + (- B) (- A) + (+B) (- A) + (- B) (+A) - (+B) (+A) - (- B) (- A) - (+B) (- A) - (- B) Add Magnitude +(A + B) - (A + B) Subtract Magnitude When A>B When A<B When A=B +(A - B) - (B - A) +(A - B) - (A - B) +(B - A) +(A - B) Hardware Implementation Bs AVF E B Register Complementer Output Carry Parallel Adder M(Mode Control) Input Carry S As Computer Organization A Register Load Sum Prof. H. Yoon

Computer Arithmetic 3 Addition and Subtraction SIGNED 2’S COMPLEMENT ADDITION AND SUBTRACTION Hardware B

Computer Arithmetic 3 Addition and Subtraction SIGNED 2’S COMPLEMENT ADDITION AND SUBTRACTION Hardware B Register Complementer and Parallel Adder V Overflow AC Algorithm Subtract Computer Organization Add Minuend in AC Subtrahend in B Augend in AC Addend in B AC + B’+ 1 V overflow AC + B V overflow END Prof. H. Yoon

Computer Arithmetic 4 Multiplication MULTIPLICATION Multiplication: B * A; B: Multiplicand; A: Multiplier; P:

Computer Arithmetic 4 Multiplication MULTIPLICATION Multiplication: B * A; B: Multiplicand; A: Multiplier; P: Partial Product Multiplication of Unsigned Positive Numbers A = An-1 An-2. . . A 0 B = Bn-1 Bn-2. . . B 0 P=B*A n-1 = B * ( 2 i * A i ) i=0 = An-1 * (B 2 n-1) + An-2 * (B 2 n-2) +. . . + A 0 * (B 20) B shifted left n-1 bits B shifted left n-2 bits B shifted left 0 bits = A Or B shifted (n-1) bits to the left P = An-1*(B 2 n-1 * 20) + An-2*(B 2 n-1 * 2 -1) +. . . + A 0*(B 2 n-1 * 2 -(n-1)) B 2 n-1 Computer Organization B 2 n-1 shifted right 1 bit B 2 n-1 shifted right (n-1) bits Prof. H. Yoon

Computer Arithmetic 5 Multiplication EXAMPLE Multiplicand B=10111 E Multiplier in Q Q 0 =

Computer Arithmetic 5 Multiplication EXAMPLE Multiplicand B=10111 E Multiplier in Q Q 0 = 1; add B First partial product Shift right EAQ Q 0 = 1; add B Second Partial Product Shift right EAQ Q 0 = 0; shift right EAQ Q 0 = 1; add B Fifth partial product Shift right EAQ Final Product in AQ = 0110110101 0 Computer Organization 0 0 1 0 0 0 A 00000 10111 010111 00010 10001 01000 00100 10111 11011 01101 Q SC 10011 101 11001 100 01100 10110 01011 010 001 10101 000 Prof. H. Yoon

Computer Arithmetic 6 Multiplication SIGNED MAGNITUDE MULTIPLICATION Bs Hardware B Register Sequence Counter Complementer

Computer Arithmetic 6 Multiplication SIGNED MAGNITUDE MULTIPLICATION Bs Hardware B Register Sequence Counter Complementer and Parallel Adder As 0 Qn Qs E AC Q Register EAQ B <- Multiplicand B Q <- Multiplier. A Algorithm As, Qs <- Qs Bs A <- 0, E <- 0 SC <- n-1 = 0 Q =1 0 EA <- A + B END Product in AQ Computer Organization =0 =0 shr EAQ SC <- SC+1 SC Prof. H. Yoon

Computer Arithmetic 7 Multiplication BOOTH MULTIPLICATION ALGORITHM FOR SIGNED 2’S COMPLEMENT Multiplier Strings of

Computer Arithmetic 7 Multiplication BOOTH MULTIPLICATION ALGORITHM FOR SIGNED 2’S COMPLEMENT Multiplier Strings of 0’s: No addition; Simply shifts Strings of 1’s: String of 1’s from mp to mq: 2 p+1 - 2 q Example 001110 (14) -> p = 3, q = 1 001110 = 23+1 - 21 M * 14 = M 24 - M 21 Algorithm [1] Subtract multiplicand for the first least significant 1 in a string of 1’s in the multiplier [2] Add multiplicand for the first 0 after the string of 1’s in the multiplier [3] Partial Product does not change when the multiplier bit is identical to the previous bit 110010 = -24 + 22 - 21 = -16 + 4 - 2 = -14 subtract 24 Add 22 Computer Organization subtract 21 Prof. H. Yoon

Computer Arithmetic 8 Multiplication BOOTH ALGORITHM FOR SIGNED 2’S COMPLEMENT B <- Multiplicand B

Computer Arithmetic 8 Multiplication BOOTH ALGORITHM FOR SIGNED 2’S COMPLEMENT B <- Multiplicand B Q <- Multiplier A AC <- 0 Q-1 <- 0 SC <- n 10 01 Q 0 Q-1 ? Q-1 : shifted out bit on shr of Q 11 00 AC<-AC+B’+1 AC <- AC + B ashr(AC&Q) SC <- SC + 1 0 SC ? =0 END Computer Organization Prof. H. Yoon

Computer Arithmetic 9 Multiplication EXAMPLE OF BOOTH MULTIPLIER Q 0 Q-1 10 B =

Computer Arithmetic 9 Multiplication EXAMPLE OF BOOTH MULTIPLIER Q 0 Q-1 10 B = 10111 B’+1=01001 Initial Subtract B 11 01 ashr Add B 00 10 ashr Subtract B ashr Computer Organization AC 00000 01001 00100 00010 10111 11001 11100 11110 01001 00111 00011 Q 10011 Q -1 0 SC 101 11001 01100 1 1 100 011 10110 01011 0 0 010 001 10101 1 000 Prof. H. Yoon

Computer Arithmetic 10 Multiplication ARRAY MULTIPLIER A = a 1 a 0: Multiplier B

Computer Arithmetic 10 Multiplication ARRAY MULTIPLIER A = a 1 a 0: Multiplier B = b 1 b 0: Multiplicand C = B * A = c 3 c 2 c 1 c 0 c 3 a 1 b 1 c 2 b 1 b 0 a 1 a 0 b 0 a 1 b 0 c 1 c 0 b 1 b 0 a 1 b 0 HA C S c 3 Computer Organization c 2 HA C S c 1 c 0 Prof. H. Yoon

Computer Arithmetic 11 Multiplication ARRAY MULTIPLIER 4 -BIT X 3 -BIT a 0 b

Computer Arithmetic 11 Multiplication ARRAY MULTIPLIER 4 -BIT X 3 -BIT a 0 b 3 b 2 b 1 b 0 a 1 b 3 b 2 b 1 b 0 0 Addend Augend 4 -bit Adder Sum and Carry Outputs a 2 b 3 b 2 b 1 b 0 Addend Augend 4 -bit Adder Sum and Carry Outputs c 6 Computer Organization c 5 c 4 c 3 c 2 c 1 c 0 Prof. H. Yoon

Computer Arithmetic 12 Division DIVISION A/B=Q+R A: Dividend; B: Divisor; Q: Quotient; R: Remainder

Computer Arithmetic 12 Division DIVISION A/B=Q+R A: Dividend; B: Divisor; Q: Quotient; R: Remainder Divisor B = 10001, B’+ 1 = 01111 E A 01110 Dividend: 0 11100 shl EAQ 01111 add B’+1 1 01011 E=1 1 01011 Set Q 0=1 0 10110 shl EAQ 01111 Add B’+1 1 00101 E=1 1 00101 Set Q 0=1 0 01010 shl EAQ 01111 add B’+1 0 11001 E=0; Q 0=0 10001 add B 1 01010 restore remainder 0 10100 shl EAQ 01111 add B’+1 1 00011 E=1 1 00011 Set Q 0=1 0 00110 shl EAQ 01111 add B’+1 0 10101 E=0; Q 0=0 10001 add B 1 00110 restore remainder neglect E 00110 remainder in A quotient in Q Computer Organization Q 00000 SC 5 000010 4 000110 3 001101 11010 2 1 11010 0 11010 Prof. H. Yoon

Computer Arithmetic 13 Division FLOWCHART OF DIVIDE OPERATION Dividend in AQ Divisor in B

Computer Arithmetic 13 Division FLOWCHART OF DIVIDE OPERATION Dividend in AQ Divisor in B Qs As Bs SC<- n - 1 shl EAQ E EA A + B’+1 1 E A B EA A+B’+1 0 A<B A A+B’+1 1 E 0(A<B) EA A+B DVF 1 EA A+B DVF 0 A B Q 0 1 EA A+B SC SC-1 END (Divide overflow) 0 SC 0 END (Quotient in Q Remainder in R) Computer Organization Prof. H. Yoon

Computer Arithmetic 14 Floating Point Arithmetic FLOATING POINT ARITHMETIC OPERATIONS F = m x

Computer Arithmetic 14 Floating Point Arithmetic FLOATING POINT ARITHMETIC OPERATIONS F = m x re where m: Mantissa r: Radix e: Exponent Registers for Floating Point Arithmetic Bs B b Parallel Adder E As A 1 Qs Computer Organization A Q BR Parallel Adder and Comparator a q AC QR Prof. H. Yoon

Computer Arithmetic 15 Floating Point Arithmetic FLOATING POINT ADD AND AUBTRACT C H E

Computer Arithmetic 15 Floating Point Arithmetic FLOATING POINT ADD AND AUBTRACT C H E C K F O R =0 BR 0 AC 0 =0 a<b AC BR add a>b a: b shr A a a+1 op sub As A’s shr B b b+1 sub 0 0 1 As B s 0 EA<-A+B’+1 A A’+1 As A’s add op 1 As B s Align Mantissa 0 0 E A A 1 1 EA A+B =0 AC 0 shl A a a+1 + or - of mantissa E Normalization shr A A 1 E a a+1 END Computer Organization Prof. H. Yoon

Computer Arithmetic 16 Floating Point Arithmetic FLOATING POINT MULTIPLICATION BR Multiplicand QR Multiplier =0

Computer Arithmetic 16 Floating Point Arithmetic FLOATING POINT MULTIPLICATION BR Multiplicand QR Multiplier =0 =0 BR 0 QR 0 AC 0 a q a a+b a a - bias Multiply mantissa (finxed point multiplication) shl AQ a a-1 0 A 1 1 END (Product is in AC) Computer Organization Prof. H. Yoon

Computer Arithmetic 17 Floating Point Arithmetic FLOATING POINT DIVISION BR Divisor AC Dividend =0

Computer Arithmetic 17 Floating Point Arithmetic FLOATING POINT DIVISION BR Divisor AC Dividend =0 =0 QR 0 BR 0 AC 0 Qs As + Bs Q 0 SC n-1 divide by 0 EA A+B’+1 1 E 0 A<B A>=B A A+B shr A a a+1 A A+B a a+b’+1 a a+bias q a Divide Magnitude of mantissa as in fixed point numbers Computer Organization Prof. H. Yoon

Computer Arithmetic 18 BCD Arithmetic BCD ADD BCD digit < 10 BCD digit +

Computer Arithmetic 18 BCD Arithmetic BCD ADD BCD digit < 10 BCD digit + carry =< 19 K 0 0 0 0 1 1 Binary Sum Z 8 Z 4 Z 2 0 0 0 0 1 0 0 1 1 1 0 0 1 0 1 1 1 1 0 0 0 0 1 Computer Organization Z 1 0 1 0 1 0 1 C 0 0 0 0 0 1 1 1 1 1 BCD Sum S 8 S 4 S 2 S 1 0 0 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 Decimal 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Prof. H. Yoon

Computer Arithmetic 19 BCD Arithmetic BCD ADDER If we can convert Binary Sums to

Computer Arithmetic 19 BCD Arithmetic BCD ADDER If we can convert Binary Sums to BCD Sum , we can use a binary adder to add two BCD numbers SUM =< 9 BCD Sum = Binary Sum BCD Carry = Binary Carry 19 >= SUM > 9 BCD Sum = Binary Sum + 0110 BCD Carry = Carry(Binary Sum + 0110) 4 -bit Binary Add 1 K 0 Take next higher digit Z 8 0 1 1 Z 4 done ? 0 1 Z 2 BCD Sum + 0110 BCD C Carry(BCD Sum) Computer Organization END 0 BCD Sum = Sum BCD C Carry(Sum) Prof. H. Yoon

Computer Arithmetic 20 BCD Arithmetic BCD ADDER HARDWARE Addend Carry Out K Augend 4

Computer Arithmetic 20 BCD Arithmetic BCD ADDER HARDWARE Addend Carry Out K Augend 4 -bit Binary Addr Z 8 Z 4 Z 2 Carry In Z 1 BCD Carry 0 0110 4 -bit Binary Adder S 8 S 4 S 2 S 1 Computer Organization Prof. H. Yoon

Computer Arithmetic 21 Decimal Arithmetic DECIMAL ARITHMETIC OPERATIONS Addition - Identical to the BCD

Computer Arithmetic 21 Decimal Arithmetic DECIMAL ARITHMETIC OPERATIONS Addition - Identical to the BCD addition - 9’s complement and 10’s complement are identical to 1’s complement and 10’s complement, respectively Computer Organization Prof. H. Yoon