Computer Architecture MIPS Instruction Set Architecture MemoryStorage Architecture

Computer Architecture MIPS Instruction Set Architecture Memory/Storage Architecture Lab

Instruction Set Architecture q q An Abstract Data Type l Objects ≡ Registers & Memory l Operations ≡ Instructions Goal of Instruction Set Architecture Design l To allow high-performance & low-cost implementations while satisfying constraints imposed by applications including operating system and complier Memory/Storage Architecture Lab 2

Instruction Set Architecture as an ADT (Review) Assumptions 8 bit ISA # of registers = 4 + PC (Program Counter) Memory size = 64 B Memory 63 63 ·· ·· Registers r 3 r 2 r 1 r 0 (sw r 3, 0(r 0)) (lw r 2, 1(r 0)) add r 1, r 2, r 3 r 2 r 1 r 0 PC 7 2 0 4 Before Register and Memory/Storage Architecture Lab 8 12 20 2 21 (j 15) (beq r 0, r 1, 2) 24 23 22 21 20 (sw r 3, 0(r 0)) (lw r 2, 1(r 0)) (add r 1, r 2, r 3) ·· 3 2 1 0 Registers (add r 1, r 2, r 3) ·· PC 8 12 1 2 20 (j 15) (beq r 0, r 1, 2) 24 23 22 21 20 3 2 1 0 7 2 0 4 After Register and Memory 3

Instruction Set Architecture as an ADT (Review) Assumptions 8 bit ISA # of registers = 4 + PC (Program Counter) Memory size = 64 B Memory 63 63 ·· ·· Registers r 3 r 2 r 1 r 0 (sw r 3, 0(r 0)) (lw r 2, 1(r 0)) lw r 2, 1(r 0) r 3 r 2 r 1 r 0 PC 7 2 0 4 Before Register and Memory/Storage Architecture Lab 8 7 20 2 22 (j 15) (beq r 0, r 1, 2) 24 23 22 21 20 (sw r 3, 0(r 0)) (lw r 2, 1(r 0)) (add r 1, r 2, r 3) ·· 3 2 1 0 Registers (add r 1, r 2, r 3) ·· PC 8 12 20 2 21 (j 15) (beq r 0, r 1, 2) 24 23 22 21 20 3 2 1 0 7 2 0 4 After Register and Memory 4

Instruction Set Architecture as an ADT (Review) Assumptions 8 bit ISA # of registers = 4 + PC (Program Counter) Memory size = 64 B Memory 63 63 ·· ·· Registers r 3 r 2 r 1 r 0 (sw r 3, 0(r 0)) (lw r 2, 1(r 0)) sw r 3, 0(r 0) r 3 r 2 r 1 r 0 PC 7 2 0 4 Before Register and Memory/Storage Architecture Lab 8 7 20 2 23 (j 15) (beq r 0, r 1, 2) 24 23 22 21 20 (sw r 3, 0(r 0)) (lw r 2, 1(r 0)) (add r 1, r 2, r 3) ·· 3 2 1 0 Registers (add r 1, r 2, r 3) ·· PC 8 7 20 2 22 (j 15) (beq r 0, r 1, 2) 24 23 22 21 20 3 2 1 0 7 8 0 4 After Register and Memory 5

Instruction Set Architecture as an ADT (Review) Assumptions 8 bit ISA # of registers = 4 + PC (Program Counter) Memory size = 64 B Memory 63 63 ·· ·· Registers r 3 r 2 r 1 r 0 (sw r 3, 0(r 0)) (lw r 2, 1(r 0)) beq r 0, r 1, 2 r 3 r 2 r 1 r 0 PC 7 8 0 4 Before Register and Memory/Storage Architecture Lab 8 7 20 2 24 (j 15) (beq r 0, r 1, 2) 24 23 22 21 20 (sw r 3, 0(r 0)) (lw r 2, 1(r 0)) (add r 1, r 2, r 3) ·· 3 2 1 0 Registers (add r 1, r 2, r 3) ·· PC 8 7 20 2 23 (j 15) (beq r 0, r 1, 2) 24 23 22 21 20 3 2 1 0 7 8 0 4 After Register and Memory 6

Instruction Set Architecture as an ADT (Review) Assumptions 8 bit ISA # of registers = 4 + PC (Program Counter) Memory size = 64 B Memory 63 63 ·· ·· Registers r 3 r 2 r 1 r 0 j 15 r 3 r 2 r 1 r 0 (add r 1, r 2, r 3) PC 7 8 0 4 Before Register and Memory/Storage Architecture Lab 8 7 20 0 15 (j 15) (beq r 0, r 1, 2) 24 23 22 21 20 (sw r 3, 0(r 0)) (lw r 2, 1(r 0)) (add r 1, r 2, r 3) ·· 3 2 1 0 Registers (sw r 3, 0(r 0)) (lw r 2, 1(r 0)) ·· PC 8 7 20 0 24 (j 15) (beq r 0, r 1, 2) 24 23 22 21 20 3 2 1 0 7 8 0 4 After Register and Memory 7

Examples of ISAs and Implementations q Instruction Set Architectures l q IBM System/360, IA-32 (x 86), IA-64, MIPS, SPARC, Alpha, PA-RISC, ARM, … Implementations l IA-32 (x 86) − − − l l Intel: 8086, 8088, 80186, 80286, 80386, 80486, Pentium Pro, Pentium II, Celeron, Pentium III, Pentium 4, … AMD: K 5, K 6 -II, K 6 -III, Athlon, Duron, … Cyrix: 80486, 5 x 86, 6 x 86, … IA-64: Itanium, Itanium 2, … Alpha: 21064, 21164, 21264, 21364, … Memory/Storage Architecture Lab 8

History q Hot topics in Computer Architecture l l l High-level language computer architectures in the 1970 s RISC architectures in the early 1980 s Shared-memory multiprocessors in the late 1980 s Out-of-order speculative execution processors in the 1990 s Multi-core architectures in the 2000 s From “Single-Chip Multiprocessors: the Rebirth of Parallel Architecture” by Prof. Guri Sohi Memory/Storage Architecture Lab 9

A Critical point in VLSI Technology Source: www. icknowledge. com Memory/Storage Architecture Lab 10

History of RISC Architecture q Integration of processors on a single chip l A critical point (“epoch”) l Argued for different architectures (RISC) − − q Small repertoire of instructions in a uniformat Pipelined execution Cache memory Load/store architecture More transistors allowed for different optimizations l Large/multi-level caches l Co-processors l Superscalar l etc From “Single-Chip Multiprocessors: the Rebirth of Parallel Architecture” by Prof. Guri Sohi Memory/Storage Architecture Lab 11

MIPS Instruction Set Architecture q One of the Pioneering RISC Instruction Set Architectures l l q q Small repertoire of instructions in a uniformat Pipelined execution Cache memory Load/store architecture Starts with a 32 -bit architecture, later extended to 64 -bit Even currently used in many embedded applications l l Game consoles – Nintendo 64, Play. Station 2, etc Network devices – IP phone, WLAN Access points, etc Residential Devices – High Definition TV, Digital Photo Frame, etc 12 Memory/Storage Architecture Lab

MIPS ISA State (Register & Memory) Register Memory 0 xffff $31 $1 $0 30 2 words = 0 32 2 bytes PC LO HI 0 x 0000 Memory/Storage Architecture Lab 13

MIPS Register Usage (Software Convention for Interoperability) 0 $zero constant 0 16 $s 0 permanent 1 $at reserved for assembler ··· 2 $v 0 return values 23 $s 7 3 $v 1 24 $t 8 temporary 4 $a 0 arguments 25 $t 9 5 $a 1 26 $k 0 OS kernel (reserved) 6 $a 2 27 $k 1 7 $a 3 28 $gp global pointer 8 $t 0 temporary 29 $sp stack pointer ··· 30 $fp frame pointer 15 $t 7 31 $ra return address (For variables in a high-level language program) Memory/Storage Architecture Lab 14

MIPS Instructions q q Arithmetic/Logic instructions Data Transfer (Load/Store) instructions Conditional branch instructions Unconditional jump instructions Memory/Storage Architecture Lab 15

MIPS Instruction Format Memory/Storage Architecture Lab 16

MIPS Integer Arithmetic Instructions Memory/Storage Architecture Lab 17

MIPS Integer Arithmetic Instructions Memory/Storage Architecture Lab 18

MIPS Logical Instructions Memory/Storage Architecture Lab 19

MIPS Data Transfer (Load/Store) Instructions Memory/Storage Architecture Lab 20

More about Loads and Stores q q All memory accesses are exclusively through loads and stores (load-store architecture) Alignment restriction − − q Word addresses must be multiples of 4 Halfword addresses must be multiples of 2 Partial word (halfword or byte) loads from memory − − Sign-extended for signed operations Zero-extended for unsigned operations Memory/Storage Architecture Lab 21

More about Loads and Stores q Big Endian vs. Little Endian a b c MSB 23 22 21 20 ( at address 20 ) d LSB d c b a 23 22 21 20 Big Endian a b c d Little Endian (Macintosh, Sun SPARC) (DEC Station 3100, Intel 80 x 86) Memory/Storage Architecture Lab 22

MIPS Conditional Branch Instructions Memory/Storage Architecture Lab 23

MIPS Unconditional Jump Instructions Memory/Storage Architecture Lab 24

MIPS Addressing Modes q Operand in instruction itself l op q Immediate addressing rs rt Immediate Operand in register l op Register addressing rs rt rd ··· funct Registers Register q Operand in Memory l op Base addressing rs rt Register Memory Address + Byte Memory/Storage Architecture Lab Halfword Word 25

MIPS Addressing Modes q Instruction in memory l op PC-relative addressing (branch) rs rt + PC l op 4 bits Memory Address Word Pseudo-direct addressing (jump) Memory Address PC ： Memory/Storage Architecture Lab Word 26

MIPS Addressing Modes q Instruction in memory l op Register (jump register) rs Memory Word Register Memory/Storage Architecture Lab 27

Addressing Modes (Many not supported in MIPS) Addressing mode Example Instruction Meaning When used Register Add R 4, R 5, R 3 Immediate or literal Add R 4, R 5, Displacement or based Add R 4, R 5, 100(R 1) R 4 ← R 5 + M[100+R 1] Accessing local variables. Register deferred or indirect Add R 4, R 5, (R 1) R 4 ← R 5 + M[R 1] Accessing using a pointer or a computed address. Indexed Add R 3, R 5, (R 1+R 2) R 3 ← R 5 + M[R 1+R 2] Sometimes useful in array addressing R 1=base of array, R 2=index amount. Direct or absolute Add R 1, R 5, (1001) R 1 ← R 5 + M[1001] Sometimes useful for accessing static data: address constant may need to be large. Memory indirect or memory deferred Add R 1, R 5, @(R 3) R 1 ← R 5 + M[M[R 3]] If R 3 is the address of a pointer p, then mode yields *p. Auto-increment Add R 1, R 5, (R 2)+ R 1 ← R 5 + M[R 2] Useful for stepping through arrays within a loop. R 2 pointers to start of array; each reference increments R 2 by size of an element, d. #3 R 4 ← R 5 + R 3 When a value is in a register. R 4 ← R 5 + For constants. 3 R 2 ← R 2 + d Auto-decrement Add R 1, R 5, -(R 2) R 2 ← R 2 - d R 1 ← R 5 + M[R 2] Same use as autoincrement. Autoincrement/decrement can also be used to implement a stack as push and pop. Scaled or index Add R 1, R 5, 100(R 2)[R 3] R 1 ← R 5 + M[100+R 2+R 3*d] Used to index arrays. May be applied to any base addressing mode in some machines. Memory/Storage Architecture Lab 28

C vs. Assembly C f = (g + h) – (i + j); Assembly add $t 0, $s 1, $s 2 add $t 1, $s 3, $s 4 sub $s 0, $t 1 f is mapped to s 0 g is mapped to s 1 h is mapped to s 2 i is mapped to s 3 j is mapped to s 4 Memory/Storage Architecture Lab 29

C vs. Assembly C g = h + A[i]; g is mapped to s 1 h is mapped to s 2 s 3 contains the base address of array A[]. i is mapped to s 4. Assembly add $t 1, $s 4 add $t 1, $t 1 add $t 1, $s 3 lw $t 0, 0($t 1) add $s 1, $s 2, $t 0 Memory/Storage Architecture Lab 30

C vs. Assembly C if (i == j) else f = g + h; f = g – h; Assembly bne $s 3, $s 4, Else add $s 0, $s 1, $s 2 j Exit Else: sub $s 0, $s 1, $s 2 Exit: f is mapped to s 0 g is mapped to s 1 h is mapped to s 2 i is mapped to s 3 j is mapped to s 4 Memory/Storage Architecture Lab 31

C vs. Assembly C Assembly while (save[i] == k) i = i + j; i is mapped to s 3 j is mapped to s 4 k is mapped to s 5 s 6 contains the base address of array save[]. Loop: add $t 1, $s 3 add $t 1, $t 1 add $t 1, $s 6 lw $t 0, 0($t 1) bne $t 0, $s 5, Exit add $s 3, $s 4 j Loop Exit: Memory/Storage Architecture Lab 32

C vs. Assembly C switch (k) { case 0: f = case 1: f = case 2: f = case 3: f = } Assembly i + j; break; g + h; break; g - h; break; i - j; break; f is mapped to s 0 g is mapped to s 1 h is mapped to s 2 i is mapped to s 3 j is mapped to s 4 k is mapped to s 5 t 2 contains 4 slt $t 3, $s 5, $zero bne $t 3, $zero, Exit slt $t 3, $s 5, $t 2 beq $t 3, $zero, Exit add $t 1, $s 5 add $t 1, $t 1 add $t 1, $t 4 lw $t 0, 0($t 1) jr $t 0 L 0: add $s 0, $s 3, $s 4 j Exit L 1: add $s 0, $s 1, $s 2 j Exit L 2: sub $s 0, $s 1, $s 2 j Exit L 3: sub $s 0, $s 3, $s 4 Exit Memory/Storage Architecture Lab 33

Pseudo Instructions q q Pseudo instruction : Instructions that are available in assembly language but not implemented in hardware Pseudo instruction examples Pseudo instruction Equivalent real instruction sequence move $s 1, $s 2 add $s 1, $zero, $s 2 blt $s 1, $s 2, label slt $at, $s 1, $s 2 bne $at, $zero, label abs $s 1, $s 2 add slt beq sub $s 1, $zero, $s 2 $at, $s 2, $zero $at, $zero, L $s 1, $zero, $s 1 L: Memory/Storage Architecture Lab 34