Computer Architecture Lecture 3 Abhinav Agarwal Veeramani V

Computer Architecture Lecture 3 Abhinav Agarwal Veeramani V.

Quick recap – Pipelining source: http: //cse. stanford. edu/class/sophomore-college/projects-00/risc/pipelining/

Quick recap – Problems n Data hazards q Dependent Instructions n n n IF ID/RF EX MEM WB Control Hazards q Branches resolution n n add r 1, r 2, r 3 store r 1, 0(r 4) bnz r 1, label add r 1, r 2, r 3 label: sub r 1, r 2, r 3 Structural Hazards IF ID/RF EX MEM WB

Data Hazards n RAW hazard – Read after Write n n n IF ID/RF EX MEM WB IF ID/RF EX MEM WAW hazard – Write after Write n n add r 1, r 2, r 3 store r 1, 0(r 4) div r 1, r 3, r 4 … add r 1, r 10, r 5 WAR hazard – Write after Read n Generally not relevant in simple pipelines WB

Remedies n n n Bypass values (Data forwarding) RAW hazards are tackled this way Not all RAW hazards can be solved by forwarding. E. g. : Load delay, What about IF ID/RF EX MEM WB divide? IF ID/RF EX MEM What is the solution? Static compiler techniques WB

Can we do better? n Execute independent executions out-oforder? What do we require for this? n n n n lw r 4, 0(r 6) addi r 5, r 4, 0 x 20 and r 10, r 5, r 19 xor r 26, r 2, r 7 sub r 20, r 26, r 2 #Cache miss - Takes time Fetch more instructions. . . Instructions should be commited in-order Memory instructions? Is dependency clear?

The WAW hazard n n Is it unavoidable? What is the reason for such hazard? Register renaming q q More physical registers Logical registers mapped to physical registers available when the instruction is decoded

Control Hazard n Branch delay slot n n n bnz r 1, label add r 1, r 2, r 3 label: sub r 1, r 2, r 3 IF ID/RF EX MEM WB Save one cycle stall. Fetch in the negative edge to save another. Deeper pipelines. Such static compiler techniques would not work.

What can be done? n n Predict if the branch will be taken or not History of each branch saved and prediction done accordingly. Example: Bimodal predictor Branch prediction is very important and complex these days due to some architectural innovations and some bottlenecks.

Bimodal predictor q q Entry: 2 -bit saturating counters Index: least significant bits of the instruction address Prediction: Combinatorial Update: When branch is resolved

Remedies to Structural hazards n n n Simplest solution: Increase resources, functional units (Silicon allows us to do this) Another solution: Pipeline the functional units Pipelining is not always possible/feasible.

Superscalar execution! n n n Execute more than one instruction every cycle. Make better use of the functional units Fetch, commit more instructions every cycle.

Memory Organization in processors n n n Caches inside the chip Faster – ‘Closer’ SRAM cells They contain recentlyused data They contain data in ‘blocks’

Rational behind caches n Principle of spatial locality n Principle of temporal locality n Replacement policy (LRU, LFU, etc. ) n Principle of inclusivity

References n n http: //en. wikipedia. org/wiki/Hazard_(compute r_architecture) http: //www. csee. umbc. edu/~plusquel/611/slid es/chap 3_3. html