Computer Architecture Lecture 20 CPU design of a

Computer Architecture （计算机体系结构) Lecture 20 CPU design (of a single-cycle CPU) Lecturer Yuanqing Cheng 2020 -10 -16

Review CPU design involves Datapath, Control Datapath in MIPS involves 5 CPU stages 1. Instruction Fetch 2. Instruction Decode & Register Read 3. ALU (Execute) 4. Memory 5. Register Write L 20 CPU Design : Designing a Single-Cycle CPU (2) Cheng, fall 2020 © BUAA

Datapath Summary ALU Data memory rd rs rt registers PC instruction memory The datapath based on data transfers required to perform instructions A controller causes the right transfers to happen imm +4 opcode, funct Controller L 20 CPU Design : Designing a Single-Cycle CPU (3) Cheng, fall 2020 © BUAA

How to Design a Processor: step-by-step 1. Analyze instruction set architecture (ISA) datapath requirements 1. 2. 3. meaning of each instruction is given by the register transfers datapath must include storage element for ISA registers datapath must support each register transfer 2. Select set of datapath components and establish clocking methodology 3. Assemble datapath meeting requirements 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. 5. Assemble the control logic L 20 CPU Design : Designing a Single-Cycle CPU (4) Cheng, fall 2020 © BUAA

Review: The MIPS Instruction Formats All MIPS instructions are 32 bits long. 3 formats: R-type 31 26 op rs 6 bits 31 I-type op 6 bits 16 rt 5 bits 26 31 J-type 21 5 bits 21 rs 5 bits 11 6 0 rd shamt funct 5 bits 6 bits 16 rt 5 bits 0 address/immediate 16 bits 26 op 6 bits 0 target address 26 bits The different fields are: op: operation (“opcode”) of the instruction rs, rt, rd: the source and destination register specifiers shamt: shift amount funct: selects the variant of the operation in the “op” field address / immediate: address offset or immediate value target address: target address of jump instruction L 20 CPU Design : Designing a Single-Cycle CPU (5) Cheng, fall 2020 © BUAA

Step 1 a: The MIPS-lite Subset for today ADDU and SUBU 31 op 6 bits addu rd, rs, rt subu rd, rs, rt OR Immediate: 31 31 sw rt, rs, imm 16 BRANCH: 31 beq rs, rt, imm 16 L 20 CPU Design : Designing a Single-Cycle CPU (6) rs 5 bits 6 bits 26 26 op 6 bits 16 rt 5 bits 21 rs op 6 bits lw rt, rs, imm 16 21 26 op ori rt, rs, imm 16 LOAD and STORE Word 26 21 rs 5 bits rd 5 bits 6 shamt 5 bits 16 rt 5 bits 11 5 bits immediate 16 bits 0 immediate 16 bits 16 rt 5 bits funct 6 bits 0 16 rt 5 bits 0 0 immediate 16 bits Cheng, fall 2020 © BUAA

Register Transfer Language (RTL) RTL gives the meaning of the instructions {op , rs , rt , rd , shamt , funct} MEM[ PC ] {op , rs , rt , Imm 16} MEM[ PC ] All start by fetching the instruction inst Register Transfers ADDU R[rd] R[rs] + R[rt]; PC + 4 SUBU R[rd] R[rs] – R[rt]; PC + 4 ORI R[rt] R[rs] | zero_ext(Imm 16); PC + 4 LOAD R[rt] MEM[ R[rs] + sign_ext(Imm 16)]; PC + 4 STORE MEM[ R[rs] + sign_ext(Imm 16) ] R[rt]; PC + 4 BEQ if ( R[rs] == R[rt] ) then PC + 4 + (sign_ext(Imm 16) || 00) else PC + 4 L 20 CPU Design : Designing a Single-Cycle CPU (7) Cheng, fall 2020 © BUAA

Step 1: Requirements of the Instruction Set Memory (MEM) instructions & data (will use one for each) Registers (R: 32 x 32) read RS read RT Write RT or RD PC Extender (sign/zero extend) Add/Sub/OR unit for operation on register(s) or extended immediate Add 4 (+ maybe extended immediate) to PC Compare registers? L 20 CPU Design : Designing a Single-Cycle CPU (8) Cheng, fall 2020 © BUAA

Step 2: Components of the Datapath Combinational Elements Storage Elements Clocking methodology L 20 CPU Design : Designing a Single-Cycle CPU (9) Cheng, fall 2020 © BUAA

Combinational Logic Elements (Building Blocks) Adder Carry. In A B Adder 32 Sum 32 Carry. Out 32 Select MUX B 32 A B 32 Y 32 OP ALU 32 MUX A 32 Result 32 L 20 CPU Design : Designing a Single-Cycle CPU (10) Cheng, fall 2020 © BUAA

ALU Needs for MIPS-lite + Rest of MIPS Addition, subtraction, logical OR, ==: ADDU SUBU ORI R[rd] = R[rs] + R[rt]; . . . R[rd] = R[rs] – R[rt]; . . . R[rt] = R[rs] | zero_ext(Imm 16). . . BEQ if ( R[rs] == R[rt] ). . . Test to see if output == 0 for any ALU operation gives == test. How? P&H also adds AND, Set Less Than (1 if A < B, 0 otherwise) ALU follows chap 5 L 20 CPU Design : Designing a Single-Cycle CPU (11) Cheng, fall 2020 © BUAA

What Hardware Is Needed? (1/2) PC: a register which keeps track of memory addr of the next instruction General Purpose Registers used in Stages 2 (Read) and 5 (Write) MIPS has 32 of these Memory used in Stages 1 (Fetch) and 4 (R/W) cache system makes these two stages as fast as the others, on average L 20 CPU Design : Designing a Single-Cycle CPU (13) Cheng, fall 2020 © BUAA

What Hardware Is Needed? (2/2) ALU used in Stage 3 something that performs all necessary functions: arithmetic, logicals, etc. we’ll design details later Miscellaneous Registers In implementations with only one stage per clock cycle, registers are inserted between stages to hold intermediate data and control signals as they travels from stage to stage. Note: Register is a general purpose term meaning something that stores bits. Not all registers are in the “register file”. L 20 CPU Design : Designing a Single-Cycle CPU (14) Cheng, fall 2020 © BUAA

Storage Element: Idealized Memory (idealized) Write Enable Address One input bus: Data In One output bus: Data Out 32 Memory word is found by: Clk Data. Out 32 Address selects the word to put on Data Out Write Enable = 1: address selects the memory word to be written via the Data In bus Clock input (CLK) The CLK input is a factor ONLY during write operation During read operation, behaves as a combinational logic block: Address valid Data Out valid after “access Cheng, time. ” fall 2020 © BUAA L 20 CPU Design : Designing a Single-Cycle CPU (15)

Storage Element: Register (Building Block) Similar to D Flip Flop except N-bit input and output Write Enable input Write Enable: Write Enable Data In N Data Out N negated (or deasserted) (0): Data Out will not change clk asserted (1): Data Out will become Data In on positive edge of clock L 20 CPU Design : Designing a Single-Cycle CPU (16) Cheng, fall 2020 © BUAA

Storage Element: Register File consists of 32 registers: Two 32 -bit output busses: bus. A and bus. B One 32 -bit input bus: bus. W Register is selected by: RWRA RB Write Enable 5 5 5 bus. W 32 Clk bus. A 32 32 32 -bit Registers bus. B 32 RA (number) selects the register to put on bus. A (data) RB (number) selects the register to put on bus. B (data) RW (number) selects the register to be written via bus. W (data) when Write Enable is 1 Clock input (clk) The clk input is a factor ONLY during write operation During read operation, behaves as a combinational logic block: RA or RB valid bus. A or bus. B valid after “access time. ” L 20 CPU Design : Designing a Single-Cycle CPU (17) Cheng, fall 2020 © BUAA

Step 3: Assemble Data. Path meeting requirements Register Transfer Requirements Datapath Assembly Instruction Fetch Read Operands and Execute Operation L 20 CPU Design : Designing a Single-Cycle CPU (18) Cheng, fall 2020 © BUAA

3 a: Overview of the Instruction Fetch Unit The common RTL operations Fetch the Instruction: mem[PC] Update the program counter: Sequential Code: PC + 4 Branch and Jump: PC “something else” clk PC Next Address Logic Address Instruction Memory L 20 CPU Design : Designing a Single-Cycle CPU (19) Instruction Word 32 Cheng, fall 2020 © BUAA

3 b: Add & Subtract R[rd] = R[rs] op R[rt] (addu rd, rs, rt) Ra, Rb, and Rw come from instruction’s Rs, Rt, and Rd 31 fields 26 21 op 6 bits rs 5 bits 16 rt 5 bits 11 rd 5 bits 6 shamt 5 bits ALUctr and Reg. Wr: control logic after decoding the. Rdinstruction Rs Rt Reg. Wr 5 5 Rw Ra Rb 32 32 -bit Registers clk ALUctr bus. A 32 bus. B ALU bus. W 32 5 funct 6 bits 0 Result 32 32 … Already defined the register file & ALU L 20 CPU Design : Designing a Single-Cycle CPU (20) Cheng, fall 2020 © BUAA

Peer Instruction 1) We should use the main ALU to compute PC=PC+4 2) The ALU is inactive for memory reads or writes. L 20 CPU Design : Designing a Single-Cycle CPU (21) a) b) c) d) 12 FF FT TF TT Cheng, fall 2020 © BUAA

How to Design a Processor: step-by-step 1. Analyze instruction set architecture (ISA) datapath requirements meaning of each instruction is given by the register transfers datapath must include storage element for ISA registers datapath must support each register transfer 2. Select set of datapath components and establish clocking methodology 3. Assemble datapath meeting requirements 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. 5. Assemble the control logic (hard part!) L 20 CPU Design : Designing a Single-Cycle CPU (22) Cheng, fall 2020 © BUAA