Computer Architecture Lecture 2 Abhinav Agarwal Veeramani V

Computer Architecture Lecture 2 Abhinav Agarwal Veeramani V.

Quick Recap n n n Various metrics in design of processor The interface & internal structure Instruction Set Architecture q q Assembly instructions Instruction encoding add r 1, r 2, r 3 000111 000010 00011

Outline n n n RISC Multi-cycle execution Pipelining

Reduced Instruction Set Computer (RISC) n n n Limited no. of instructions Fixed Length Simple to decode Easier to implement in hardware Prevalent in all commercial processors at the core level Counterpart – C(omplex)ISC q q q Intel processors Multi-operation instructions Still Intel processors have switched to RISC at second level

Execution Cycle of a RISC Instruction Five main phases of Instruction Lifecycle IF: Instruction Fetch 1. n n Read Instruction Memory at PC Bring the instruction into the CPU ID/RF: Instruction Decode/Register Fetch 2. n n Translate the opcode of the instruction to appropriate control signals No. of operands Registers clearly specified in instruction code Fetch operand values from the registers

Execution Cycle of a RISC Instruction EX: ALU computation 3. § § Activate appropriate functional unit – Adder, Multiplier, Divider, Logical Unit Why no Subtracter? MEM: Memory Operation 4. n Load/Store data from/to Data Memory WR: Register Write 5. n Write the final result value into register

A Picture speaks a thousand words

Multi Cycle Execution Cycle Per Instruction (CPI) Kinds of Implementation: n n 1. One cycle for each stage q q 2. Cycle time determined by longest stage CPI = ? Combine all stages into a single cycle q q Cycle time determined by worst case instruction CPI = 1

Execution Snapshot: Cycle 1 IF PC 00010 Instr 00000 Mov r 2, 2 A 00001 Mov r 3, 12 00010 Add r 1, r 2, r 3 00011 Store r 1, 0(r 4) 00100 XXXX 00101 XXXX 000111 000010 00011 Address

Execution Snapshot: Cycle 2 ID/RF PC 00011 00001 Mov 00010 add 00011 Store 00100 XXXX 00101 XXXX r 2, Mov r 1, 00000 Add Instr r 3 000111 000010 00011 Address Reg Data r 1 12 H r 2 2 A H r 3 12 H r 4 00 H r 5 01 H

Execution Snapshot: Cycle 3 EX PC 00011 00001 Mov 00010 add 00011 Store 00100 XXXX 00101 XXXX r 2, Mov r 1, 00000 Add Instr r 3 000111 000010 00011 Address Reg Data r 1 12 H r 2 2 A H r 3 12 H r 4 00 H r 5 01 H 12 Adder 2 A

Execution Snapshot: Cycle 4 MEM PC 00011 00001 Mov 00010 add 00011 Store 00100 XXXX 00101 XXXX r 2, Mov r 1, 00000 Add Instr r 3 000111 000010 00011 Address Reg Data r 1 12 H r 2 2 A H r 3 12 H r 4 00 H r 5 01 H 12 2 A Adder ? ?

Execution Snapshot: Cycle 5 WB PC 00011 00001 Mov 00010 add 00011 Store 00100 XXXX 00101 XXXX r 2, Mov r 1, 00000 Add Instr r 3 000111 000010 00011 Address Reg Data r 1 3 C H r 2 2 A H r 3 12 H r 4 00 H r 5 01 H Adder

Execution Snapshot: Cycle 1 IF PC 00011 00001 Mov 00010 add 00011 Store 00100 XXXX 00101 XXXX 0(r 4) Mov r 1, 00000 store Instr 111001 00100 00000 Address

Instruction Execution Timeline n n n Sequential Execution Low utilization of functional units Alternative ? store r 1, 0(r 4) add r 1, r 2, r 3 IF ID/ RF EX ME WB M IF ID/ RF EX ME M Instruction Execution Timeline IF ID/ RF EX ME WB M

Pipelining: Concept and Example n Washing machine, Dryer, Iron source: http: //cse. stanford. edu/class/sophomore-college/projects-00/risc/pipelining/

Pipelining Concept n Remarkable Insight or Common Sense Time Savings: Per person 0% Overall 42% source: http: //cse. stanford. edu/class/sophomore-college/projects-00/risc/pipelining/

Implementation of Pipelining in RISC n n n Parallelism in all 5 stages New instruction every cycle Best case scenario Inst IF Time ID/RF EX MEM WB IF ID/RF EX MEM WB

Hardware Requirements source: http: //cse. stanford. edu/class/sophomore-college/projects-00/risc/pipelining/

Problems n Data hazards q Dependent Instructions n n n IF ID/RF EX MEM WB Control Hazards q Branches resolution n n add r 1, r 2, r 3 store r 1, 0(r 4) bnz r 1, label add r 1, r 2, r 3 label: sub r 1, r 2, r 3 Structural Hazards IF ID/RF EX MEM WB

References n Wikipedia: CPU Parallelism http: //en. wikipedia. org/wiki/Central_processing_unit#Parallelism n http: //www. cs. iastate. edu/~prabhu/Tutorial/PIPELINE/pipe_title. html