Computer Architecture Basics of Datapath MemoryStorage Architecture Lab

Computer Architecture Basics of Datapath Memory/Storage Architecture Lab

Combinational Logic Elements q Stateless logic l l l No embedded state (memory) Output fully dependent on inputs Any function possible AND, OR, NAND, NOR, XOR, NOT… − AND OR NOT Memory/Storage Architecture Lab 2

Combinational Logic Elements q Adder q ALU 4 ALU control input Function 0000 AND 0001 OR 0010 add 0110 subtract 0111 set on less than Memory/Storage Architecture Lab 3

Combinational Logic Elements q Multiplexor l A two-input multiplexor l A 32 -bit wide 2 -to-1 multiplexor 0 1 Memory/Storage Architecture Lab 4

Storage Elements q Register l Similar to the D Flip Flop except N-bit input and output −Write Enable input − l Write Enable : 0 : Data Out will not change − 1 : Data Out will become Data in − l Stored data changes only on falling clock edge! Memory/Storage Architecture Lab 5

Storage Elements q Register File consists of 32 registers: l Two 32 -bit output busses: − l l q One 32 -bit input bus: Write data Register 0 hard-wired to value 0 Register numbers Data Register is selected by: l l l q Read data 1 and Read data 2 5 Read register 1 5 Read register 2 5 Write register Write data Read data 1 Registers Data Read data 2 Reg. Write Read register 1 selects the register to put on Read data 1 Read register 2 selects the register to put on Read data 2 Write register selects the register to be written via write data when Reg. Write = 1 Clock input (CLK) l The CLK input is a factor only for write operation (data changes only on falling clock edge) Memory/Storage Architecture Lab 6

Storage Elements Mem. Write q Memory has two busses: l l q Address selects l l q One output bus : Read data (Data Out) One input bus : Write data (Data In) Address Read data Data In Write data Memory Mem. Read the word to put on Data Out when Mem. Read = 1 the word to be written via the Data In when Mem. Write = 1 Clock input (CLK) l The CLK input is a factor only for write operation (data changes only on falling clock edge) Memory/Storage Architecture Lab 7 Data Out

Clocking q All storage elements clocked by the same clock edge l l l Edge-triggered clocking (falling clock edge) One clock period per clock cycle Design always works if the clock is “slow enough” Cycle Time = tprop + tcombinational + tsetup + tskew Memory/Storage Architecture Lab 8

add Instruction 31 26 op 6 bits 21 rs 5 bits 000000 q add rd, rs, rt IR ← mem[PC]; R[rd] ← R[rs] + R[rt]; PC ← PC + 4; 16 rt 5 bits 11 rd 5 bits 6 0 shamt 5 bits funct 6 bits 00000 100000 RTL Description Fetch instruction from memory ADD instruction Calculate next address Memory/Storage Architecture Lab 9

sub Instruction 31 26 op 6 bits 21 rs 5 bits 000000 q sub rd, rs, rt IR ← mem[PC]; R[rd] ← R[rs] + ~R[rt] + 1; PC ← PC + 4; 16 rt 5 bits 11 rd 5 bits 6 0 shamt 5 bits funct 6 bits 00000 100010 RTL Description Fetch instruction from memory SUB instruction Calculate next address Memory/Storage Architecture Lab 10

lw Instruction 31 26 op 6 bits 21 rs 5 bits 16 rt 5 bits 0 immediate 16 bits 100011 q lw rt, rs, imm 16 IR ← mem[PC]; Addr ← R[rs] + Sign. Ext(imm 16); R[rt] ← Mem[Addr]; PC ← PC + 4; RTL Description Fetch instruction from memory Compute memory address Load data into register Calculate next address Memory/Storage Architecture Lab 11

sw Instruction 31 26 op 6 bits 21 rs 5 bits 16 rt 5 bits 0 immediate 16 bits 101011 q sw rt, rs, imm 16 IR ← mem[PC]; Addr ← R[rs] + Sign. Ext(imm 16); Mem[Addr] ← R[rt]; PC ← PC + 4; RTL Description Fetch instruction from memory Compute memory address Store data into memory Calculate next address Memory/Storage Architecture Lab 12

beq Instruction 31 26 op 6 bits 21 rs 5 bits 16 rt 5 bits 0 immediate 16 bits 000100 q beq rt, rs, imm 16 RTL Description IR ← mem[PC]; Fetch instruction from memory Cond ← R[rs] + ~R[rt] + 1; Compute conditional Cond if (Cond == 0) then PC ← PC + 4 + (Sign. Ext(imm 16) << 2); (Branch if equal) else PC ← PC + 4; (Fall through otherwise) Memory/Storage Architecture Lab 13

Instruction Format Summary q Add, sub, and, or l l q rd, rs, rt 26 21 16 11 6 0 op rs rt rd shamt funct 6 bits 5 bits 6 bits R-format Instruction Load, store l l q add sub 31 lw sw rt, rs, imm 16 31 Branch l beq 26 21 16 op rs rt 6 bits 5 bits 0 imm 16 16 bits I-format Instruction rt, rs, imm 16 Memory/Storage Architecture Lab 14

PC-Related Datapath Memory/Storage Architecture Lab 15

Datapath for R-format Instructions 4 Memory/Storage Architecture Lab 16

Datapath for a Load or Store 4 Memory/Storage Architecture Lab 17

Datapath for a Branch 4 Memory/Storage Architecture Lab 18

R-type + (Load or Store) 4 Memory/Storage Architecture Lab 19

R-type + (Load or Store) + Branch 4 Memory/Storage Architecture Lab 20