Computer Architecture and Design ELEC 52006200 Class Project

Computer Architecture and Design ELEC 5200/6200 Class Project Overview Director: Dr. Vishwani D. Agrawal GTA: Jia Yao (jzy 0001@auburn. edu) 1 Fall 2011

Outline �The Goal – What are you going to design? �The Software �The Hardware �Evaluation of your project �Demo 2 Fall 2011

The Goal – What are you going to design? �Design a CPU �basic arithmetic operations: add (+), subtract (-) �basic logical operations: AND, OR, NOT �control flow structures: “ifelse” structures, “while” loops and “for” loops �relational operators: ==, !=, >, ≥, <, ≤ �Functions: call and return �Halt 3 Control Datapat h Central Processing Unit (CPU) or “processor” Input Memor y Output Fall 2011

4 Datapa th Examp Sign ext. Shift left 2 Memto. Reg Mem. Write Mem. Read Data mem. 0 mux 1 zero 0 mux 1 ALU 1 mux 0 Branch Reg. File Instr. mem. 1 mux 0 PC opcode CONTROL Reg. Dst Add 4 1 mux 0 Jump Shift left 2 ALU Cont. Fall 2011

PC Altera DE 2 Board Download your design and test program What to do on Altera Board: What to do on PC: (4) Test and debug the (1)Design your CPU downloaded design (2)Simulate your design in Modelsim (5) Run test programs in a (3) Synthesize and download your properly working CPU design into Altera Board by Quartus II 5 Fall 2011

�CPU design project consists of five parts �Part 1 – design an instruction set architecture (ISA): 6 define registers, instruction set �Part 2 – design datapath that realizes your ISA: make a choice from single-cycle, multi-cycle or pipeline ? �Part 3 – datapath verification: programming and simulation �Part 4 – design control unit: Fall 2011 based on your choice of datapath

The Software �Programming: VHDL/Verilog �each component in the datapath is programmed in VHDL/Verilog. �Simulation: Modelsim 6. 6 b �verification of logic functions. �Hardware implementation: Altera Quartus II 10. 0 �synthesis, timing analysis, design optimization and configuration of Altera FPGA board. 7 * Modelsim and Quartus II are available in Broun 320 Lab Fall 2011

The Hardware �Altera Development and Education Board (DE 2) �Control and Datapath: Altera Cyclone II FPGA �Clock: 27 MHz and 50 MHz oscillators �Input: Pushbutton switches and toggle switches �Output: LEDs and 7 -Segment Displays �Memory: 512 Kbyte SRAM, 8 Mbyte SDRAM, 4 Mbyte Flash Memory; Mega-function Plug-in �Configuring the board in JTAG mode or Active Serial mode 8 Fall 2011

Altera DE 2 Board 9 Fall 2011

Active Serial Configuration Scheme � “PROG” ON – Configure EPCS 16 device by selecting configuration bit stream file (. pof file) in Quartus II Programmer tool. � “RUN” ON – Reset the board; this action cause configuration data in EPCS 16 device to be loaded onto the FPGA. � Data is retained in EPCS 16 device even when power. Fallis 2011 10 turned off; when power is turned back on, data is

The Evaluation �A simple test program will be given to you in part 5, and you are encouraged to write your own test program. �Conduct a five-minute demo of the implemented design on your DE 2 Board as follows: �Briefly describe the program you will run and the expected results. �Run the program with proper explanation of the buttons you press and results 11 Fall 2011

Demo � Addi $s 1, 2 % $s 1=2, $s 1 * $s 2 = 2*4 � Addi $s 2, 3 %$s 2=4 � Addi $s 6, $s 6 7 % $s 6=7 � L 1: Add $s 5, $s 1 %$s 5= result of loop of addition � Addi $s 2, -1 % $s 2=$s 2 -1 � Beq $s 2, $zero, Exit % if $s 2=0, end of loop � Jump L 1 % continue loop � Exit: sw $s 5, 7($s 6) % Memory($s 6+7) = Registers Initial Value Expected Value $s 5 s 1 0 2 � Halt s 2 % program 1 0 stops 12 s 5 0 8 s 6 0 7 Fall 2011

Questions? 13 Fall 2011

References (1) Altera Corporation, “Altera DE 2 User Manual”, http: //www. altera. com/education/univ/materials/boards/de 2/unv-de 2 board. html (2) Altera Corporation, “Intruduction to Mega. Wizard Plug-In”, http: //www. altera. com/products/ip/altera/megawizd. html (3) Auburn University ELEC 5200 class website, “Altera Quartus II and DE 2 Manual”, http: //www. eng. auburn. edu/~vagrawal/COURSE/E 6200_Fall 10/HW/HW 3/Alte ra%20 Quartus%20 II%20 and%20 DE 2%20 manual. pdf (4) Auburn University ELEC 5200 class website, “Altera Megawizard Plug-In Manager Manual ” (5) Auburn University ELEC 5200 class website, “Run time content editable memory tutorial”, http: //www. eng. auburn. edu/~vagrawal/COURSE/E 6200_Fall 10/HW/HW 3/Run _time_content_editable_memory_tutorial. pdf 14 Fall 2011