Computer Architecture A Constructive Approach Six Stage PipelineBypassing

Computer Architecture: A Constructive Approach Six Stage Pipeline/Bypassing Joel Emer Computer Science & Artificial Intelligence Lab. Massachusetts Institute of Technology March 14, 2012 http: //csg. csail. mit. edu/6. S 078 L 11 -1

Three-Cycle SMIPS: Analysis Decode/Reg. Read/ Execute/Memory Fetch pc Fetch ir Writeback wr Decode/Reg. Read/ Execute/Memory mr Writeback Does Fetch or DRXM depend on Writeback? Yes, for register values March 14, 2012 http: //csg. csail. mit. edu/6. S 078 L 11 -2

Stall calculation WB Stall Reg WB Feedback Stall calculation wb. Stall March 14, 2012 http: //csg. csail. mit. edu/6. S 078 L 11 -3

Data dependence waterfall From whiteboard March 14, 2012 http: //csg. csail. mit. edu/6. S 078 L 11 -4

Types of Data Hazards Consider executing a sequence of instructions like: rk (ri) op (rj) Data-dependence r 3 (r 1) op (r 2) r 5 (r 3) op (r 4) Read-after-Write (RAW) hazard Anti-dependence r 3 (r 1) op (r 2) r 1 (r 4) op (r 5) Write-after-Read (WAR) hazard Output-dependence r 3 (r 1) op (r 2) r 3 (r 6) op (r 7) Write-after-Write (WAW) hazard March 14, 2012 http: //csg. csail. mit. edu/6. S 078 L 11 -5

Detecting Data Hazards Range and Domain of instruction i R(i) = Registers (or other storage) modified by instruction i D(i) = Registers (or other storage) read by instruction i Suppose instruction j follows instruction i in the program order. Executing instruction j before the effect of instruction i has taken place can cause a RAW hazard if WAR hazard if WAW hazard if March 14, 2012 R(i) D(j) D(i) R(j) R(i) R(j) http: //csg. csail. mit. edu/6. S 078 L 11 -6

Register vs. Memory Data Dependence Data hazards due to register operands can be determined at the decode stage but Data hazards due to memory operands can be determined only after computing the effective address store load M[(r 1) + disp 1] (r 2) r 3 M[(r 4) + disp 2] Does (r 1 + disp 1) = (r 4 + disp 2) ? March 14, 2012 http: //csg. csail. mit. edu/6. S 078 L 11 -7

Data Hazards: An Example I 1 DIVD f 6, f 4 I 2 LD f 2, 45(r 3) I 3 MULTD f 0, f 2, f 4 I 4 DIVD f 8, f 6, f 2 I 5 SUBD f 10, f 6 I 6 ADDD f 6, f 8, f 2 RAW Hazards WAR Hazards WAW Hazards March 14, 2012 http: //csg. csail. mit. edu/6. S 078 L 11 -8

Scoreboard R 31 • • • Register#(Bit#(32)) R 0 scoreboard <- mk. Reg(0); Add a scoreboard of registers in use: n n n March 14, 2012 Set bit for each register to be updated Clear bit when a register is updated Stall if bit for a register needed is set http: //csg. csail. mit. edu/6. S 078 L 11 -9

SMIPs Pipeline Analysis Stage Tclock > Six stage March 14, 2012 Fetch t. M Decode t. DEC Register Read t. RF Execute t. ALU Memory t. M Writeback t. WB http: //csg. csail. mit. edu/6. S 078 L 11 -10

Six Stage Pipeline Fetch Decode Reg Read p c Execute Memory Writeback w b F f r D d r R r r X x r M m r W Where do we need feedback? X to F and W to R March 14, 2012 http: //csg. csail. mit. edu/6. S 078 L 11 -11

Six-Stage State module mk. Proc(Proc); Reg#(Addr) fetch. Pc RFile rf Memory mem FIFO#(FBundle) FIFO#(Dec. Bundle) FIFO#(Reg. Bundle) FIFO#(EBundle) FIFO#(WBundle) fr dr rr xr mr FIFOF#(Addr) next. Pc FIFOF#(Rindx) wb. Rind <- mk. Reg. U; <- mk. RFile; <- mk. Memory; <<<<<- mk. FIFO; <- mk. FIFOF; // and internal control state… March 14, 2012 http: //csg. csail. mit. edu/6. S 078 L 11 -12

Six-Stage Fetch rule do. Fetch; Addr pc = ? ; Bool epoch = fetch. Epoch; if (next. Pc. not. Empty) begin pc = next. Pc. first; epoch = !fetch. Epoch; next. Pc. deq; end else pc = fetch. Pc + 4; fetch. Pc <= pc; fetch. Epoch <= epoch; let inst. Resp <- mem. op(Mem. Req{op: Ld, addr: pc, data: ? }); fr. enq(FBundle{pc: pc, epoch: epoch, Inst. Resp: inst. Resp}); endrule March 14, 2012 http: //csg. csail. mit. edu/6. S 078 L 11 -13

Six-Stage Decode rule do. Decode; let fetch. Inst = fr. first; let pc. Plus 4 = fetch. Inst. predpc + 4; let dec. Inst = decode(fetch. Inst. inst. Resp, pc. Plus 4); dec. Inst. epoch = fetch. Inst. epoch; dr. enq(dec. Inst); fr. deq; endrule March 14, 2012 http: //csg. csail. mit. edu/6. S 078 L 11 -14

Register Read Stage Reg Read Decode D Decode RF must be available to Read. Srcs and Writeback! March 14, 2012 d r R r r W Read regs RF http: //csg. csail. mit. edu/6. S 078 L 11 -15

Register Read Module typedef struct { Data: src 1; Data: src 2 } Sources; module mk. Reg. Read#(RFile rf)(Reg. Read); Reg#(Bool) scoreboard. Reg <- mk. Reg(False); Dwire#(Bool) scoreboard <-mk. Dwire(scoreboard. Reg); rule update. Scoreboard; scoreboard. Reg <= scoreboard; endrule method Maybe#(Sources) read. Regs(Decode. Inst dec. Inst); let src 1 = rf. rd 1(dec. Inst. op 1); let src 2 = … if (scoreboard. Reg) return tagged Invalid; else return tagged Valid Sources{src 1: src 1, …}; endmethod March 14, 2012 http: //csg. csail. mit. edu/6. S 078 L 11 -16

Register Read Module typedef struct { Data: src 1; Data: src 2 } Sources; module mk. Reg. Read#(RFile rf)(Reg. Read); Reg#(Bool) scoreboard. Reg <- mk. Reg(False); method Maybe#(Sources) read. Regs(Decode. Inst dec. Inst); let src 1 = rf. rd 1(dec. Inst. op 1); let src 2 = … if (scoreboard. Reg) return tagged Invalid; else return tagged Valid Sources{src 1: src 1, …}; endmethod To use need to instantiate with: let readreg <- mk. Read. Reg(rf); March 14, 2012 http: //csg. csail. mit. edu/6. S 078 L 11 -17

Six-Stage Register Read (cont) RWire#(Bool) next_available <-mk. RWire; RWire#(Bool) next_unavailable <- mk. RWire; method mark. Available(); next_available. wset(False); endmethod mark. Unavailable(); next_unavailable. wset(True); endmethod rule update. Scoreboard; if (next_unavailable matches tagged Valid. ua) scoreboard. Reg <= True; else if (next_available matches tagged Valid. a) scoreboard. Reg <= False; endrule endmodule March 14, 2012 http: //csg. csail. mit. edu/6. S 078 L 11 -18

Six-Stage Register Read rule do. Reg. Read; if (wb. Rind. not. Empty) begin readreg. mark. Available(); wb. Rind. deq; end let dec. Inst = dr. first(); if (exec. Epoch != dec. Inst. epoch) begin readreg. mark. Available(); dr. deq() end; else begin maybe. Sources = readregs. read. Regs(dec. Inst); if (maybe. Sources match tagged Valid. sources) begin if (writesreg(dec. Inst)) rr. mark. Unavailable(); rr. enq(Reg. Bundle{decodebundle: dec. Inst, src 1: srouces. src 1, src 2: sources. src 2}); dr. deq(); end Better scoreboard will need register index! endrule March 14, 2012 http: //csg. csail. mit. edu/6. S 078 L 11 -19

Six-Stage Execute rule do. Execute; let dec. Inst = rr. first. decodebundle; let epoch. Change = (dec. Inst. epoch != exec. Epoch); let src 1 = rr. first. src 1; let src 2 =. . . if (! epoch. Change) begin let exec. Inst = exec(dec. Inst, src 1, src 2); if (exec. Inst. cond) begin next. Pc. enq(exec. Inst. addr); exec. Epoch <= !exec. Epoch; end xr. enq(exec. Inst); end rr. deq(); endrule March 14, 2012 http: //csg. csail. mit. edu/6. S 078 L 11 -20

Six-Stage Memory rule do. Memory; let exec. Inst = xr. first; if (exec. Inst. itype==Ld || exec. Inst. itype==St) begin exec. Inst. data <- mem(Mem. Req{ op: exec. Inst. itype==Ld ? Ld : St, addr: exec. Inst. addr, data: exec. Inst. data}); end mr. enq(WBBundle{itype: exec. Inst. itype, rdst: exec. Inst. rdst, data: exec. Inst. data}); xr. deq(); endrule March 14, 2012 http: //csg. csail. mit. edu/6. S 078 L 11 -21

Six-Stage Writeback rule do. Write. Back; wb. Rind. enq(mr. first. rdst); rf. wr(mr. first. rdst, mr. first. data); mr. deq; endrule March 14, 2012 http: //csg. csail. mit. edu/6. S 078 L 11 -22

Six Stage Waterfall From whiteboard March 14, 2012 http: //csg. csail. mit. edu/6. S 078 L 11 -23

Bypass Reg. Read rr Execute What does Reg. Read need to do? If scoreboard says register is not available then Reg. Read needs to stall, unless it sees what it needs on the bypass line…. March 14, 2012 http: //csg. csail. mit. edu/6. S 078 L 11 -24

Bypass Network typedef struct { Rindx regnum; Data value; } Bypass. Value; Module mk. Bypass(Bypass. Network) Rwire#(Bypass. Value) bypass; method produce. Bypass(Rindx regnum, Data value); bypass = Bypass. Value{regname: regnum, value: value}; endmethod Maybe#(Data) consume. Bypass(Rindx regnum); if (bypass matches tagged Valid. b && b. regnum == regnum) return tagged Valid b. value; else return tagged Invalid; endmethod endmodule Real network will have many sources. How are they ordered? March 14, 2012 From earlier stages to later http: //csg. csail. mit. edu/6. S 078 L 11 -25

Register Read (with bypass) module mk. Reg. Read#(RFile rf, Bypass. Network bypass)(Reg. Read); method Maybe#(Sources) read. Regs(Decode. Inst dec. Inst); let src 1 = rf. rd 1(dec. Inst. op 1); let src 2 = … if (!scoreboard. Reg) return tagged Valid Sources{src 1: src 1, …}; else begin let b 1 = bypass. consumebypass(dec. Inst. op 1); let b 2 = if (b 1 matches tagged Valid. v 1 && b 2 matches…) return tagged Valid Sources{src 1: v 1. value …); else return tagged Invalid; endmethod March 14, 2012 http: //csg. csail. mit. edu/6. S 078 L 11 -26