Compensation for Measurement Errors Due to Mechanical Misalignments

Compensation for Measurement Errors Due to Mechanical Misalignments in PCB Testing Anura P. Jayasumana, Yashwant K. Malaiya, Xin He, Colorado State University Kenneth P. Parker and Stephen Hird Agilent Technologies

Objective • Identification of outlier boards using Capacitive Lead Frame Testing data • Improve the accuracy of outlier detection by compensating for systematic errors such as mechanical misalignment and fixture-to-fixture variations BTW 2010 2

Outline § PCA Based Outlier Detection § Test Data for Mechanical Misalignments § PCA Based Compensation § Summary BTW 2010 3

Capacitive Lead Frame Testing BTW 2010 Ref: Parker & Hird, ITC 2007 4

Example: Capacitance vs. Pin Number (for a J 245) BTW 2010 5

Principal Component Analysis (PCA) § 1 st Principal Component Measurement 2 1 st PC 2 nd PC contains largest variance from the data projection § 2 nd Principal Component, orthogonal to the 1 st one, contains second largest projected variance § Useful for analyzing multi- 0 Measurement 1 BTW 2010 dimensional data interrelated 6

PCA for PCB Outlier Detection Singular Value Decomposition Mc = USVT where, Umxn A scaled version of PC scores Snxn Diagonal matrix with square roots of Eigen values VTnxn V Z = M c. V in descending order Eigen vectors (PCs). Transformation Matrix with z-score values of boards Z-scores of a board are linear combination of all corresponding measurements for that board BTW 2010 8

Test Statistic for Outlier Detection zik : Value of the kth PC for ith board E : a subset of PCs - most significant PCs are used here § Sort the boards with respect to d 1 § Plot cumulative distribution function (CDF) of d 1 § Outliers clearly identifiable on right side of plot, typically separated from others by a clear margin BTW 2010 9

PCA Based Outlier Detection • Treats data holistically • Outlier detection as opposed to threshold based detection Board run numbers on CDF plot from left to right: 52, 51, 50, 53, 49, 32, 73, 24, 48, 25, 74, 72, 83, 71, 57, 47, 1, 42, 56, 70, 6, 68, 37, 58, 43, 59, 41, 39, 55, 40, 2, 23, 78, 33, 35, 44, 69, 79, 54, 75, 36, 64, 80, 76, 31, 77, 65, 60, 29, 81, 63, 61, 62, 3, 67, 66, 82, 27, 45, 28, 46, 26, 30, 34, 12, 8, 7, 10, 9, 16, 11, 13, 14, 15, 4, 5, 17, 22, 19, 18, 20, 21 ITC 2009 10

Capacitive Lead Frame Testing Ref: Parker & Hird, ITC 2007 • Capacitance < 100 f. F (<10 f. F with opens faults) • Systematic variations, e. g. , variations in connector height, co-planarity of ball connections, sense plate, … • Relatively small mechanical variations can lead to larger measurement variability (Ex. 18 f. F variation across shift test cases vs. std deviation of <1 f. F) • Test values and test limits set now may fail if mechanical variations appear later BTW 2010 11

Mechanical Misalignments BTW 2010 Setup Left or right End Tilt Height (mils) Setup Vertical Shift Height (mils) Tilt_0 0 Shift_0 0 Tilt_1 8 Shift _1 8 Tilt_2 16 Shift_2 16 Tilt_3 24 Shift_3 24 12

Raw measurements for B 1 with one normal and three left tilted sense plates Tilt_0 Tilt_1 Tilt_2 Tilt_3 BTW 2010

Raw measurements with normal and vertical shifted sense plate for board B 5 connector J 3 Shift_0 Shift_1 Shift_2 BTW 2010 Shift_3

Compensating for Tilt BTW 2010 15

Raw measurements with normal and vertical shifted sense plate for board B 5 connector J 3 Shift_0 Shift_1 Shift_2 BTW 2010 Shift_3

Plot of PC values for Shift Data Note: • PC-1 can be used to identify the amount of shift or tilt in sense plate • Unlike visual inspection, PCA can identify complex but systematic patterns • If the same board is tested in multiple fixtures, it may be possible to identify differences and compensate for them BTW 2010

Adjusted capacitances by setting all but 1 st PC equal to 0 for data B 1 • PC-1 captures the tilt information as well as other common information BTW 2010

Data set including two synthetic traces, Def_1 and Def_2 simulating open faults on pins 121 and 165 BTW 2010

Adjusted capacitances by setting only 1 st PCs to 0 BTW 2010

Data set including two synthetic traces, Def_1 and Def_2 simulating open faults on pins 75 and 165 BTW 2010

Adjusted capacitance by setting all but 1 st PC to zero BTW 2010

Adjusted data based on setting only 1 st PC to 0 BTW 2010

Summary § A PCA based technique presented for identification and compensation for measurement errors introduced due to sense-plate variations § Method can be used to separate misalignment related information from defect related information in test data § Approach is NOT sensitive to the order of the pins, and thus shows promise for complex but systematic errors introduced by sense plate misalignments § Method applicable to other kinds of test data BTW 2010 24

Future Work § Overcome variations caused by measurement errors, mechanical and electrical tolerances § Adaptive and learning techniques for detection and diagnosis BTW 2010 25