Comparing the SHARC and HAMMERHEAD DSPs Prepared by

Comparing the SHARC and HAMMERHEAD DSPs Prepared by Eugene So

To be tackled today n Comparison of Processor Architectures n n n ADSP 2106 X (SHARC) ADSP 2116 X (HAMMERHEAD) Focus on the advantages of the Hammerhead n n n SIMD Engine Benchmark CRISP requirements 9/29/2020 Comparing the SHARC and HAMMERHEAD 2

SHARC Architecture 9/29/2020 Comparing the SHARC and HAMMERHEAD 3

Hammerhead Architecture 32 -bit PMA bus (vs 24 -bit) 48/64 -bit PMD bus (vs 48 -bit) 40/64 -bit DMD bus (vs 40 -bit) Dual processor, Shared memory 9/29/2020 Comparing the SHARC and HAMMERHEAD 4

Single Instruction Multiple Data Engine n “The Hammerhead is a SHARC” with two CPUs n The same instruction is executed in both CPUs, but each CPU operates on different data n n n CPU 1 can be controlled CPU 2 simply performs the same operation as CPU 1 on the next memory location. This is called a Single Instruction Multiple Data (SIMD) Engine 9/29/2020 Comparing the SHARC and HAMMERHEAD 5

Advantages of SIMD n Double cycle performance n n If an algorithm can be broken into 2 components then CPU 1 can process memory elements 1, 3, 5, 7 etc. , and CPU 2 can process 2, 4, 6, 8 etc. Examples: n FIR, divide, inverse square root, matrix multiply 9/29/2020 Comparing the SHARC and HAMMERHEAD 6

FIR example n y(n) = summation from k=0 to M of h(k) * x(n-k) /* HAMMER HEAD CODE SEGMENT. . . */ lcntr=samples, do macs until lce; /* FIR loop */ macs: f 12=f 0*f 4, f 8=f 8+f 12, f 0=dm(sample_pt, m 3), f 4=pm(coeff_pt, m 9); /* (2 samples) * (2 coeffs), accum, read 2 samples, read 2 coeffs */ n Cycle count n n Hammerhead: TAPS/2 + 16 SHARC: TAPS + 9 9/29/2020 Comparing the SHARC and HAMMERHEAD 7

Advantages of SIMD (cont. ) n Double Bandwidth n n Accessing two memory locations in a single instruction essentially doubles the bandwidth between memory and the CPUs Special Addressing Modes n n n The data busses are widened to 64 -bits on the Hammerhead to accommodate SIMD One addressing mode on the Hammerhead allows identical data to be copied into both register files Another allows 64 -bit data to be split between the two register files 9/29/2020 Comparing the SHARC and HAMMERHEAD 8

Advantages of SIMD (cont. ) n Complex Arithmetic Handling n n CPU 1 handles real component CPU 2 handles imaginary component 9/29/2020 Comparing the SHARC and HAMMERHEAD 9

Complex Vector Add example n z(n) = x(n) + jy(n) /* HAMMERHEAD CODE SEGMENT */ #include "def 21160. h" /* Symbol Definition File */ . global cx_vec_add; /* program memory code */. section/pm seg_pmco; cx_vec_add: bit set MODE 1 PEYEN; /* SIMD enabled */ lcntr=samples, do add until lce; f 0=dm(i 0, m 0), f 4=pm(i 8, m 8); add: f 8=f 0+f 4, dm(i 1, m 0)=f 8; /* f 0 = Xr, s 0 = Xi, f 4 = Yr, s 4 = Yi */ /* f 8 = Xr + Yr, s 8 = Xi + Yi, store result */ rts (db); bit clr MODE 1 PEYEN; dm(i 1, m 0)=f 8; 9/29/2020 /* SIMD disabled */ /* store last result */ Comparing the SHARC and HAMMERHEAD 10

Benchmark 9/29/2020 Comparing the SHARC and HAMMERHEAD 11

CRISP Requirements 9/29/2020 Comparing the SHARC and HAMMERHEAD 12

Conclusion n n “The Hammerhead is a SHARC” with two CPUs Two heads are (usually) better than one! But also more costly! 9/29/2020 Comparing the SHARC and HAMMERHEAD 13