Combinations of Resistors Series Parallel PHY 202 Blum

Combinations of Resistors Series, Parallel PHY 202 (Blum) 1

Analyzing a combination of resistors circuit n n n 2 Look for resistors which are in series (the current passing through one must pass through the other) and replace them with the equivalent resistance (Req = R 1 + R 2). Look for resistors which are in parallel (both the tops and bottoms are connected by wire and only wire) and replace them with the equivalent resistance (1/Req = 1/R 1 + 1/R 2). Repeat as much as possible. PHY 202 (Blum)

Look for series combinations Req=3 k Req=3. 6 k 3 PHY 202 (Blum)

Look for parallel combinations Req = 1. 8947 k Req = 1. 1244 k 4 PHY 202 (Blum)

Look for series combinations Req = 6. 0191 k 5 PHY 202 (Blum)

Look for parallel combinations Req = 2. 1314 k 6 PHY 202 (Blum)

Look for series combinations Req = 5. 1314 k 7 PHY 202 (Blum)

Equivalent Resistance I = V/R = (5 V)/(5. 1314 k ) = 0. 9744 m. A 8 PHY 202 (Blum)

Backwards 1 V= (3)(. 9744) = 2. 9232 V= (2. 1314)(. 9744) = 2. 0768 9 PHY 202 (Blum)

Backwards 2 V = 2. 0768=I (3. 3) I=0. 629 m. A 10 PHY 202 (Blum) V = 2. 0768=I (6. 0191) I=0. 345 m. A

Backwards 3 V=(. 345)(3)=1. 035 V=(. 345)(1. 8947)=0. 654 V=(. 345)(1. 1244)=0. 388 11 PHY 202 (Blum)

Multiplexing and Demultiplexing In some sense, Multiplexing and Demultiplexing is just a special case of the truth tables we have been studying. You can look under “multiplexor” and “decoder” in the index of Tokheim for more information. 12 PHY 201 (Blum)

Getting Around n n A fair amount of what goes on inside computers or on computer networks just involves moving data (as opposed to processing that data). Most designs have shared information channels (a bus). n n 13 Part of the path used to get from Point A to Point B may also be along the way from Point C to Point D. Multiplexing and demultiplexing concerns selecting the data to be transmitted and directing the data to its destination. PHY 201 (Blum)

Multiplexing n n Multiplexing is sending more than one signal on a carrier. There are two standard types of multiplexing. n n 14 Frequency-Division Multiplexing (FDM): the medium carries a number of signals, which have different frequencies; the signals are carried simultaneously. Time-Division Multiplexing (TDM): different signals are transmitted over the same medium but they do so at different times – they take turns. PHY 201 (Blum)

Mutiplexing Multiplexing allows one to select one of the many possible sources. 15 PHY 201 (Blum)

Statistical TDM n n n 16 In standard TDM, the inputs take turns, one after the other gets to put its information onto the wire. In Statistical TDM, the input with the most data or highest priority gets a higher share of the time. In this course, our wires hold a single bit of information at a time, so we will focus on a simple type of TDM. It will be somewhat more like statistical TDM in that we will be choosing which input places its information on the wire. PHY 201 (Blum)

Multiplexing n There are several data inputs and one of them is routed to the output (possibly the shared communication channel). n n In addition to data inputs, there must be select inputs. n n The select inputs determine which data input gets through. How many select pins are needed? n 17 Like selecting a television channel (although that example is FDM). Depends on number of data inputs. PHY 201 (Blum)

Addresses n n 18 All of the (data) inputs at hand are assigned addresses. The address of the data input is used to select which data input is placed on the shared channel. So in addition to the collection of data inputs, there are selection (or address) inputs that pick which of the data inputs gets through. PHY 201 (Blum)

How many? n n 19 One bit can have two states and thus distinguish between two things. Two bits can be in four states and … Three bits can be in eight states, … N bits can be in 2 N states 0 0 0 1 1 0 1 0 1 1 0 0 1 1 1 PHY 201 (Blum)

Nomenclature n n n A Multiplexer is also known as a MUX. A MUX has several data inputs and one data output. If the MUX has N (possible) data inputs, it is referred to as an N-to-1 MUX. n n 20 Since computers work in binary, the N is usually a power of 2. An N-to-1 MUX should have log 2(N) address inputs (pins). PHY 201 (Blum)

Log 2(N) 21 N 2 4 8 Log 2(N) 1 2 3 N 512 1024 2048 Log 2(N) 9 10 11 16 32 64 128 256 4 5 6 7 8 4096 8192 16384 32768 65536 12 13 14 15 16 PHY 201 (Blum)

Combinatorial Logic n n n 22 A MUX uses combinatorial logic (as opposed to a sequential logic which involves memory). The output of a MUX depends solely on the data input and the select input. Thus it is just the realization of a truth table. PHY 201 (Blum)

Truth table for 2 -to-1 MUX Select When A=0, Out is same as D 0, when A=1, Out is same as D 1 23 Data A D 0 D 1 Out 0 0 0 1 0 1 1 0 0 0 1 1 1 1 0 0 1 1 PHY 201 (Blum)

Algebra for 2 -to-1 MUX n n Take expressions for 1’s found in truth table A D 0 D 1 + AD 0 D 1 n n A D 0(D 1 +D 1) + A(D 0 +D 0)D 1 n n (D 1 +D 1) = 1 Not D 1 or D 1, doesn’t care about D 1 Note that this factoring/reducing requires the two terms to differ by only one input. A D 0 + AD 1 n 24 This can be factored as follows (A more general technique for simplifying Boolean expressions uses the Karnaugh map. ) PHY 201 (Blum)

Karnaugh Version 25 A BS 0 1 0 0 0 1 1 1 1 0 PHY 201 (Blum)

Gates for 2 -to-1 MUX 26 PHY 201 (Blum)

4 -to-1 MUX: truth table Select Data Out A B D 0 D 1 D 2 D 3 0 0 D 1 D 2 D 3 D 0 0 1 1 1 0 1 D 0 D 0 D 1 D 1 D 2 D 2 D 3 D 3 D 1 D 2 D 3 D 0 could be a 1 or a 0, but if A=0 and B=0 then Out is whatever D 0 is. 27 PHY 201 (Blum)

4 -to-1 MUX: gate version One output Many inputs 28 PHY 201 (Blum)

Addresses n Each data input is assigned to a specific state of the select input. n n The state can be interpreted as binary numbers n n n 29 E. g. low-low, low-high, high-low, high-high 00, 01, 10, 11 Two select Four addresses And these numbers are thought of as the “addresses” of the input. PHY 201 (Blum)

Demultiplexing n n If any of several signals was put onto a single carrier, then at the other end the signals must be separated and each sent to the appropriate destination. One input (the shared channel) is routed to one of several outputs. n n In addition to data input, there must be select inputs. n 30 Like mail, it is possible for me to send a message to any individual one of you. So there must be a set of paths from me to each of you, and there must be a mechanism for selecting one of those paths in a particular instance. To select from 2 N data outputs requires N select inputs. PHY 201 (Blum)

Demultiplexing allows one to select one of the many possible destinations. 31 PHY 201 (Blum)

Nomenclature n n Demultiplexer a. k. a. De. MUX. A De. MUX has one data input and several outputs. n n 32 If the De. MUX has N (possible) data outputs, it may referred to as an 1 -to-N De. MUX. Since computers work in binary, the N is usually a power of 2. An 1 -to-N De. MUX should have log 2(N) address inputs (pins). De. MUX are also sometimes referred to by the number of address pins log 2(N)-to-N De. MUX (e. g. 3 -to-8 or 2 -to-4 De. MUX) PHY 201 (Blum)

Combinatorial Logic n n n 33 A De. MUX has many outputs. Each of those outputs depends only on the input data and the select data (i. e. no memory is involved). Thus a De. MUX is just a realization of a truth table (as is all combinatorial logic). PHY 201 (Blum)

1 -to-4 De. Mux: Truth table Select 34 Data Output S 1 S 0 A O 0 O 1 O 2 O 3 0 0 0 0 0 1 1 0 0 1 0 0 1 1 0 0 0 1 PHY 201 (Blum)

1 -to-4 De. MUX: gate version (may also be called 2 -to-4) Many outputs One input 35 PHY 201 (Blum)

Decoder n n A variation on the previous circuit is to have no input data. The selected output will be high, the others low. n n 36 Or vice versa. This can be used to activate a control pin on the selected part of circuit. PHY 201 (Blum)

2 -to-4 Decode: Truth table Select 37 Output S 1 S 0 O 1 O 2 O 3 0 0 0 1 1 0 0 0 0 1 PHY 201 (Blum)

2 -to-4 Decode: gates 38 PHY 201 (Blum)

Decoder plus registers = RAM n A register is a unit of memory that holds one word of data. n n 39 A typical word may be 32 or 64 bits. E. g. the Memory Address Register (MAR) holds an address associated with memory Memory (RAM), on the other hand, is a large collection of registers to hold the values of many different words. In addition to the registers is a decoder. The decode determines which word one is writing to or reading from. PHY 201 (Blum)

Decoder plus registers = RAM Load pins (allow data into a register) Only one location selected. MAR Decoder MAR: Memory Address register holds address one is writing to or reading from 40 Addressable set of registers PHY 201 (Blum) MDR Memory data register holds data being written to or being read from memory.

ROM is Combinatorial n n In ROM (Read Only Memory), one inputs an address and gets a predetermined output for that address. The same input always yields the same output. ROM is the realization of a truth table. ROM is a way to realize a generic truth table. n 41 In a way the opposite of what we do with a Karnaugh map. With a K-map we take a specific output and simplify it as much as possible. With ROM, we leave it as generic as possible. PHY 201 (Blum)

The logic of ROM fuse Address lines “Burned” Decoder 42 fuse PHY 201 (Blum)

Logic of ROM (Cont. ) n n n 43 Fuses connect output of decoder to output of ROM. Normal voltage and current does not burn (“blow”) the fuse. So when the selected decoder output is high, all ROM output lines to which it is connected are also high. PHY 201 (Blum)

Logic of ROM (Cont. ) n n 44 Higher voltage and current will break the connections (a. k. a. burning). They are applied selectively to break certain connections. The ROM output is not affected by the decoder output if the connection is broken. (Implementation may be different, but this is the basic logic). PHY 201 (Blum)