COE 341 Data Computer Communications Dr Marwan AbuAmara
COE 341: Data & Computer Communications Dr. Marwan Abu-Amara Chapter 6: Digital Data Communications Techniques
Contents 1. 2. 3. Asynchronous and Synchronous Transmission Types of Errors Error Detection a. b. Parity Check Cyclic Redundancy Check (CRC) COE 341 – Dr. Marwan Abu-Amara 2
Asynchronous and Synchronous n. Transmission: To communicate meaningful data serially between TX n and RX, signal timing should be the same at both Timing considerations include: q q q n n Rate Duration Spacing Need to synchronize RX to TX Two ways to achieve this: q q Asynchronous Transmission Synchronous Transmission • RX needs to sample the received data at mid-points • So it needs to establish: - Bit arrival time - Bit duration COE 341 – Dr. Marwan Abu-Amara 3
Need for RX and TX Synchronization: Transmitter Receiver RX Clock TX Clock n n n Clock drift (example): q If the receiver clock drifts by 1% every sample time, q For Tb = 1 msec, total drift after 50 bit intervals = 50 X 0. 01 = 0. 5 msec q i. e. instead of sampling at the middle, the receiver will sample bit # 50 at the edge of the bit q RX and TX clocks are out-of-synch Communication Error! In general, # of correctly sampled bits = 0. 5 Tb/(n/100)Tb = 50/n, where n is the % timing error between TX and RX Two approaches for correct reception: Tb q Send only a few bits (e. g. a character) at a time (that RX can sample correctly before losing sync) Asynchronous Transmission q Keep receiver clock synchronized with the transmitter clock Synchronous Transmission COE 341 – Dr. Marwan Abu-Amara 4
Asynchronous Transmission: Character. Level Synchronization n n Avoids the timing problem by NOT sending long, uninterrupted streams of bits. So data is transmitted one character at a time: q q q n n n Has a distinct start bit Consists of only 5 to 8 bits (so drift will not be a serious problem) Has a distinct stop bit Character is delimited (at start & end) by known signal elements: start bit – stop element Sync needs to be maintained only for the duration of a character The receiver has a new opportunity to resynchronize at the beginning of next character Timing errors do not accumulate from character to character COE 341 – Dr. Marwan Abu-Amara 5
Asynchronous Transmission (Min) Binary 1 RX waits for a character following the end of the previous character Receive Stop element Binary 1 RX “knows” how many bits To expect in a character, and keeps counting them following the ‘start’ bit • The ‘stop’ element confirms end of character otherwise: Framing Error • Stop elements continue (idling) until next character Receive Start bit S 1 Receive Stop element S 2 S 1: receiver in idling state S 2: receive in receiving state Parity bit: Even or Odd parity? COE 341 – Dr. Marwan Abu-Amara 6
Asynchronous Transmission Framing error n n Erroneous detection of end/start of a character Can be caused by: q Noise: (1 is the idling ‘stop’ bit) 1111011111… Erroneous ‘Start’ bit due to noise q Incorrect timing of bit sampling due to drift of RX clock affects bit count COE 341 – Dr. Marwan Abu-Amara 7
Asynchronous Transmission Errors due to lack of sync for an 8 -bit system n Let data rate = baud rate = 10 kbps n Bit interval = 1/10 k = 100 ms n Assume RX’s clock is faster than TX by 6% (i. e. RX thinks the bit interval is 94 ms) n RX checks mid-bit data at 47 ms and then at 94 ms intervals n Bit 8 is wrongly sampled within bit 7 (bit 7 read twice!) n Possibility of a framing error at the end (Timing for ideal sampling at RX) 100 ms 47 ms 94 ms Half the bit interval from the ‘start’ rising edge 893 COE 341 – Dr. Marwan Abu-Amara 8
Asynchronous Transmission: Efficiency n Uses 1 start bit & 2 stop bits: (i. e. 3 non-data bits) with 8 -bit characters and no parity: Efficiency = 8/(8+3) = 72% Overhead = 3/(8+3) = 28% COE 341 – Dr. Marwan Abu-Amara 9
Asynchronous Transmission – Pros & Cons Advantages: n n n Simple Cheap Good for data with large gaps (keyboard) Cons: n Overhead of 2 or 3 bits per character (~20%) n Timing errors accumulate for large character sizes COE 341 – Dr. Marwan Abu-Amara 10
Synchronous Transmission: Bit-Level Synchronization n Allows transmission of large blocks of data n n (frames) TX and RX Clocks must be synchronized to prevent timing drift Ways to achieve bit-level sync: q Use a separate clock line between TX and RX n n q Good over short distances Subject to transmission impairments over long distances Embed clock signal in data n n e. g. Manchester or Differential Manchester encoding Or carrier frequency for analog signals COE 341 – Dr. Marwan Abu-Amara 11
Synchronous Frame Format Typical Frame Structure 8 -bit control field flag Preamble bit pattern: Indicates start of frame data field control field 8 -bit flag Data field: data to be exchanged Control fields: convey control information between TX and RX Preamble/Postamble flags ensure frame-level synchronization COE 341 – Dr. Marwan Abu-Amara Postamble bit pattern: Indicates end of frame 12
Synchronous Transmission: Efficiency n Example: HDLC scheme uses a total of 48 bits for control, preamble, and postamble fields per frame: With a data block consisting of 1000 characters (8 -bits per character), Efficiency = 8000/(8000+48) = 99. 4% Overhead = 48/8048 = 0. 6% n Higher efficiency and lower overhead compared to asynchronous COE 341 – Dr. Marwan Abu-Amara 13
Errors in Digital Transmission n n Error occurs when a bit is altered between transmission and reception (0 1 or 1 0) Two types of errors: q Single bit errors n n n q Burst errors n n n One bit altered Isolated incidence, adjacent bits not affected Typically caused by white noise Contiguous sequence of B bits in which first, last, and any number of intermediate bits are in error Caused by impulse noise or fading (in wireless) More common, and more difficult to handle Effect is greater at higher data rates What to do about these errors: q q Detect them (at least, so we can ask TX to retransmit!) Correct them (if we can) COE 341 – Dr. Marwan Abu-Amara 14
Error Detection & Correction: Motivation n Assume NO error detection or correction: Number of erroneous frames received would be unacceptable 1 A frame of F bits 2 3 4 Prob [2 nd bit in error] = BER Prob [2 nd bit correct] = 1 -BER n … F-2 F-1 F 101010001010… 001 Prob [1 st bit in error] = BER Prob [1 st bit correct] = 1 -BER n … All bits must be Correct! Prob [Fth bit in error] = BER Prob [Fth bit correct] = 1 -BER Hence, for a frame of F bits, Prob [frame is correct] = (1 -BER)F : Decreases with increasing BER & F Prob [frame is erroneous] = 1 - (1 -BER)F = Frame Error Rate (FER) COE 341 – Dr. Marwan Abu-Amara 15
Motivation for Error Detection & Correction: Example n n n ISDN specifies a BER = 10 -6 for a 64 kbps channel Frame size F = 1000 bits What is the FER? q n n FER = 1 – (1 – BER)F = 1 – (0. 999999)1000 = 10 -3 Assume a continuously used channel How many frames are transmitted in one day of frames/day = (64, 000/1000) × 24 × 3600 Number = 5. 5296 × 106 n How many erroneous frames/day? q n n 5. 5296 × 10 -3 = 5. 5296 × 103 Typical requirement: Maximum of 1 erroneous frame /day! i. e. frame error rate is too high! We definitely need error detection & correction COE 341 – Dr. Marwan Abu-Amara 16
Frame Error Probabilities: 101010001010… 001 P 1 Correct 900 P 3 n n 1 - P 1 1000 100 Erroneous Errors, Detected 80 P 2 With an error detection facility Errors, Undetected 20 P 1 + P 2 + P 3 = 1 Without error detection facility: P 3 = 0, and: P 2 = 1 – P 1 COE 341 – Dr. Marwan Abu-Amara 17
Error Detection Techniques n Two main error detection techniques: q q n Parity Check Cyclic Redundancy Check (CRC) Both techniques use additional bits that are added to the “payload data” by the transmitter for the purpose of error detection COE 341 – Dr. Marwan Abu-Amara 18
Error Detection: Implementation Mismatch: Error Detected COE 341 – Dr. Marwan Abu-Amara 19
Parity Check n n Simplest error-detection scheme Appending one extra bit: q q n Example: If an even-parity is used, RX will check if the total number of 1’s is even q n Even Parity: Will append “ 1” such that the total number of 1’s is even Odd Parity: Will append “ 1” such that the total number of 1’s is odd If it is not error occurred Note: even number of bit errors go undetected COE 341 – Dr. Marwan Abu-Amara 20
Cyclic Redundancy Check (CRC) n n n Burst errors will most likely go undetected by a simple parity check scheme Instead, a more elaborate technique called Cyclic Redundancy Check (CRC) is typically implemented CRC appends redundant bits to the frame trailer called Frame Check Sequence (FCS) q n FCS is later utilized at RX for error detection In a given frame containing n bits, we define: q q q k = number of original data bits (n – k) = number of bits in the FCS field (i. e. additional bits) So, that the total frame length is k + (n – k) = n bits D (k) T(n) FCS (n-k) 1 0 0 0 1 1 0 COE 1 341 – Dr. Marwan 01110 Abu-Amara 21
CRC Generation n CRC generation is all about finding the FCS given the data (D) and a divisor (P) D (k) T (n) FCS or F (n-k) 1010001101 01110 110101 n P (n-k+1) There are three equivalent ways to generate the CRC code: q q q Modulo-2 Arithmetic Method Polynomial Method Digital Logic Method COE 341 – Dr. Marwan Abu-Amara 22
Modulo 2 Arithmetic n n n Binary arithmetic without carry Equivalent to XOR operation i. e: q q n 0 0 = 0; 1 0 = 1; 0 1 = 1; 1 1 = 0 1 0 = 0; 0 1 = 0; 1 1 = 1 Examples: 1010 +1010 ______ 0000 COE 341 – Dr. Marwan Abu-Amara 23
CRC Error Detection Process n n Given k-bit data (D), the TX generates an (n – k)-bit FCS field (F) such that the total n-bit frame (T) is exactly divisible by some (n-k+1)-bit predetermined devisor (P) (i. e. gives a zero remainder) In general, the received frame may or may not be equal, in value, to the sent frame q q n Let the received frame be (T’) In error-free transmission T’ = T The RX then divides (T’) by the same known divisor (P) and checks if there is any remainder q q If division yields a remainder then the frame is erroneous If the division yields zero remainder then the frame is errorfree unless many erroneous bits in T’ resulted in a new exact division by P n (This is very unlikely but possible, causing an undetected error!) COE 341 – Dr. Marwan Abu-Amara 24
CRC Generation T = 2 (n – k) D + F (n-k) left shifts (multiplications by 2) Data D: ? LSB • P is 1 -bit longer than F COE 341 – Dr. Marwan Abu-Amara 25
CRC Generation n n T = 2(n – k) D + F, What is F that makes T divides P exactly ? Claim: F is the remainder obtained from dividing {2(n – k) D} by divisor P (1) n where Q is the quotient and F is the remainder If this is the correct F, T should now divide P with Zero remainder n Note: For F to be a remainder when dividing by P, it should be 1 -bit smaller COE 341 – Dr. Marwan Abu-Amara 26
CRC Generation – Modulo-2 Arithmetic Method n At TX: CRC Generation (using previous rules): q q q n Multiply: 2(n – k) D (left shift by (n-k) bits) Divide: 2(n – k) D / P Use the resulting (n – k)-bit remainder as the FCS At RX: CRC Checking: RX divides the received T (i. e. T’) by the known divisor (P) and checks if there is any remainder COE 341 – Dr. Marwan Abu-Amara 27
Example – Modulo-2 Arithmetic n. Method Given q q n n D=1010001101 P=110101 Find the FCS field Solution: q First we note that: n n The size of the data block D is k = 10 bits The size of P is (n – k + 1) = 6 bits Hence the FCS length is n – k = 5 Total size of the frame T is n = 15 bits COE 341 – Dr. Marwan Abu-Amara 28
Example – Modulo-2 Arith. Method n Solution (continued): q Multiply 2(n – k) D n n q 2(5) 1 0 0 0 1 1 0 1 = 1 0 0 0 1 1 0 0 0 This is a simple shift to the left by five positions Divide 2(n – k) D / P (see next slide for details) n 1 0 0 0 1 1 0 0 0 ÷ 1 1 0 1 yields: q q Quotient Remainder Q=1101010110 R=01110 So, FCS = R = 0 1 1 1 0: Append it to D to get the full frame T to be transmitted T=101000110101110 M FCS COE 341 – Dr. Marwan Abu-Amara 29
Example – Modulo-2 Arith. Method # of bits < # of bits in P, result of division is 0 Checks you should do (exercise): - Verify correct operation, i. e. that 2(n-k)D = P*Q + R - Verify that obtained T (101000110101110) divides P (110101) exactly (i. e. with zero remainder) COE 341 – Dr. Marwan Abu-Amara = FCS = F 30
Problem 6 -12 n For P = 110011 & D = 11100011, find the CRC COE 341 – Dr. Marwan Abu-Amara 31
n n n n Chances of missing an error by CRC error detection Let E be an n-bit number with a bit = 1 at the position of each error bit error occurring in T Error occurring in T causes bit reversal Bit reversal is obtained by XORing with 1 So, received Tr = T E Error is missed (not detected) if Tr is divisible by P Since T is made divisible by P, this requires that E is also divisible by P!. That is a ‘bit’ unlikely! COE 341 – Dr. Marwan Abu-Amara 32
n CRC Generation – Polynomial Method A k-bit word (D) can be expressed as a polynomial D(x) of degree (k-1) in a dummy variable x, with: q q The polynomial coefficients being the bit values The powers of X being the corresponding powers of 2 bk-1 bk-2 … b 2 b 1 b 0 bk-1 Xk-1 + bk-2 Xk-2 + … + b 1 X 1 + b 0 X 0 where bi (k-1 ≤ i ≤ 0) is either 1 or 0 n Example 1: an 8 bit word D = 11011001 is represented as D(X) = x 7+x 6+x 4+x 3+1 q Ignore polynomial terms corresponding to 0 bits in the number COE 341 – Dr. Marwan Abu-Amara 33
CRC – Mapping Binary Bits into n. Polynomials Example 2: What is x 4 D(x) equal to? x 4 D(x) = x 4(x 7+x 6+x 4+x 3+1) = x 11+x 10+x 8+x 7+x 4, the equivalent bit pattern is 110110010000 (i. e. four zeros appended to the right of the original D pattern) n Example 3: What is x 4 D(x) + (x 3+x+1)? x 4 D(x) + (x 3+x+1) = x 11+x 10+x 8+x 7+x 4+ x 3+x+1, the equivalent bit pattern is 11011011 (i. e. pattern 1011 = x 3+x+1 appended to the right of the original D pattern) COE 341 – Dr. Marwan Abu-Amara 34
CRC Generation: The Polynomial Way Polynomial Binary Arithmetic n T = 2(n – k) D + F n T(X) = X(n – k) D(X) + F(X) COE 341 – Dr. Marwan Abu-Amara 35
CRC Calculation - Procedure 1. 2. 3. 4. Shift pattern D(X), (n-k) bits to the left, i. e. perform the multiplication X(n-k)D(X) Divide the new pattern by the divisor P(X) The remainder of the division, R(X) (i. e. n-k bits), is taken as FCS The frame to be transmitted T(X) is X(n -k)D(X) + FCS COE 341 – Dr. Marwan Abu-Amara 36
Example of Polynomial Method q q n n D = 1 0 0 0 1 1 0 1 (k = 10) P= 1 1 0 1 (n – k + 1 = 6) n–k=5 n = 15 Find the FCS field Solution: q q q D(X) = X 9 + X 7 + X 3 + X 2 + 1 P(X) = X 5 + X 4 + X 2 + 1 X 5 D(X)/P(X) = (X 14 + X 12 + X 8 + X 7 + X 5)/(X 5 + X 4 + X 2 + 1) n n n This yields a remainder R(X) = X 3 + X 2 + X (details on next slide) i. e. F = 01110 R is n – k = 5 -bit long Remember to indicate any 0 bits! COE 341 – Dr. Marwan Abu-Amara 37
Example of Polynomial Method F=R D T 1010001101 P 01110 110101 Insert 0 bits to m COE 341 – Dr. Marwan Abu-Amara ake 5 bit s 38
Choice of P(X) n n How should we choose the polynomial P(X) (or equivalently the divisor P)? The answer depends on the types of errors that are likely to occur in our communication link As seen before, an error pattern E(X) will be undetectable only if it is divisible by P(X) It can be shown that all the following error types are detectable : q q q All single-bit errors, if P(X) has two terms or more All double-bit errors, if P(X) has three terms or more Any odd number of errors, if P(X) contains the factor (X+1) Any burst error whose length is less than the FCS length (n – k) A fraction (=1 -2 -(n-k-1) ) of error bursts of length (n-k+1) A fraction (=1 -2 -(n-k) ) of error bursts of length > (n-k+1) COE 341 – Dr. Marwan Abu-Amara 39
Choice of P(X) n In addition, if all error-patterns are equally likely, and r = n - k = length of the FCS, then: q q n For a burst error of length (r + 1), the probability of undetected error is 1/2(r – 1) For a longer burst error i. e. length > (r + 1), the probability of undetected error is 1/2 r FCS is 1 -bit There are four widely-used versions of P(X) q q shorter than P: CRC-12: P(X) = X 12 + X 11 + X 3 + X 2 + X + 1 (r = 13 -1 = 12) FCS Size CRC-16: P(X) = X 16 + X 15 + X 2 + 1 (r = 17 -1 = 16) CRC-CCITT: P(X) = X 16 + X 12 + X 5 + 1 CRC-32: P(X) = X 32 + X 26 + X 23 + X 22 + X 16 + X 12 + X 11 + X 10 + X 8 + X 7 + X 5 + X 4 + X 2 + X + 1 (r = 33 -1 = 32) P(X) always starts with 1 COE 341 – Dr. Marwan Abu-Amara 40
Some CRC Applications n n n CRC-8 and CRC-10 (not shown) are used in ATM CRC-12 is used for transmission of 6 -bit characters. Its FCS length is 12 -bits CRC-16 & CRC-CCITT are used for 8 -bit characters in the US and Europe respectively q n Used in HDLC CRC-32 is used for IEEE 802. 3 LAN standard COE 341 – Dr. Marwan Abu-Amara 41
CRC Generation – Digital Logic • k = 10 (size of D) (known data to be TXed) • n – k + 1 = 6 size of P (known divisor) P (X) = X 5+X 4+X 2+1 (110101) • n – k = 5 size of FCS (to be determined at TX) • n = 15 • 5 -element left-shift register • Initially loaded with 0’s • After n left shifts, register will contain the required FCS Data Block, D 1010001101 Always An XOR at C 0 P = X 5+X 4+X 2+X 0 • Divisor is “hardwired” as feedback connections via XOR gates into the shift register cells • Starting at LSB, for the first (n-k) bits of P, add an XOR only for 1 bits COE 341 – Dr. Marwan Abu-Amara 42
CRC Generation at TX P = X 5+X 4+X 2+X 0 C 4 in C 2 in C 0 in Start with Shift Register Cleared to 0’s MSB D Inputs formed with Combination Logic MSB FCS generated in the shift register after n (=15) shift steps. COE 341 – Dr. Marwan Abu-Amara 43
CRC Checking at RX P = X 5+X 4+X 2+X 0 C 4 in Start with Shift Register Cleared to 0’s C 2 in C 0 in MSB FCS Received Frame, T D D 15 bits Inputs formed with Combination Logic 0’s in the shift register after n (=15) shift steps (if no errors) COE 341 – Dr. Marwan Abu-Amara 44
Problem 6 -13 • a) b) c) A CRC is constructed to generate a 4 -bit FCS for an 11 -bit message. The generator polynomial is X 4+X 3+1 Draw the shift register circuit that would perform this task Encode the data bit sequence 10011011100 (leftmost bit is the LSB) using the generator polynomial and give the code word Now assume that bit 7 (counting from the LSB) in the code word is in error and show that the detection algorithm detects the error COE 341 – Dr. Marwan Abu-Amara 45
Problem 6 -13 – Solution Input data a) C 3 C 2 C 1 b) Data (D) = 1 0 0 1 1 1 0 0 D(X) = 1 + X 3 + X 4 + X 6 + X 7 + X 8 X 4 D(X) = X 12 + X 11 + X 10 + X 8 + X 7 + X 4 C 0 P(X) = X 4+X 3+1 LSB c) T(X) = X 4 M(X) + R(X) = X 12 + X 11 + X 10 + X 8 + X 7 + X 4 + X 2 Code =001010011011100 Code in error = 0 0 1 1 0 0 yields a nonzero remainder error is detected COE 341 – Dr. Marwan Abu-Amara 46
Error Correction n n Once an error is detected, what action can RX take? (i. e. I found an error, now what? ) Two alternatives: q q RX asks for a retransmission of the erroneous frame n Adopted by data-link protocols such as HDLC and transport protocol such as TCP n A Backward Error Correction (BEC) method RX attempts to correct the errors if enough redundancy exists in the received data n TX uses Block Coding to allow RX to correct potential errors n A Forward Error Correction (FEC) method n Use in applications that leave no time for retransmission, e. g. Vo. IP. COE 341 – Dr. Marwan Abu-Amara 47
Error Correction vs. Error Control n Backward error correction by retransmission is not recommended in the following cases: q Error rate is high (e. g. wireless communication) n q Transmission distance is long (e. g. satellite, submarine optical fiber cables) n n Will cause too much retransmission traffic network overloading Network becomes very inefficient (Not utilized properly) Usually: q q Error Correction methods: Those that use FEC techniques Error Control methods: Those that use retransmission COE 341 – Dr. Marwan Abu-Amara 48
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