Code Construction and FPGA Implementation of a LowErrorFloor

Code Construction and FPGA Implementation of a Low-Error-Floor Multi-Rate Low-Density Parity-Check Code Decoder Lei Yang, Hui Liu, C. -J Richard Shi Transactions on Circuits and Systems 2006

Outline Code Design and Rates n Log-BP and MSC n FUs n Result n Conclusion n Comment n

Code Design and Rates n Regular rate 5/8 code ¨ N=149 x 82 = 9536 ¨ M=3 x 8 x 149 = 3576 n Regular rate 7/8 code ¨ N=17 x 242 = 9792 ¨ M=3 x 24 x 17 = 1224 n Irregular rate 1/2 code ¨ N=251 x 36 = 9036 ¨ M=18 x 251 = 4518

Code n Regular code ¨ ¨ H 3 consists of randomly located permutation matrix.

Irregular Code Nb x L = 36 x 251 Mb x L =18 x 251

Log-BP n Check Node Computation ¨ ¨ n Variable Node Computation ¨

Min-Sum with Correction n Check Node Computation ¨ ¨ ¨ n Variable Node Computation

Finite Precision (6: 3)

CNU (4 CU)

VNU

Architecture

Nb x L = 36 x 251 Mb x L

Result n n 40 Mbps @ 100 MHz (24 iterations) 15 Mbps @ 100 MHz (60 iterations)

Conclusion Offer a configurable 9 -kbit multi-rate LDPC decoder. (00, 01 and 10 can work at rate 1/2, 5/8 and 7/8 respectively) n Archive BER 10 -5 @ 1. 4 d. B when irregular 1/2 is operating. n

Comment Min-Sum with Correction vs. Scaling Min. Sum n Irregular Code Decoding n Rate compatible Decoder n

Comparison Ours (96 x) Presented (36 x) N Rate Algorithm 12288 9036 1/2 , (5/8 and 7/8) Scaling min-sum Min-sum with correction Memory 12288*(4*6+1) 307, 200 bit 59. 48 MHz 117*512*7 + 4. 5 K*32 1, 859, 328 bit 100 MHz Fmax Throughput 203 Mbps Gain 10 -5 at 1. 6 15 Mbps (64 Mbps) 10 -5 at 1. 4 (block error rate 10 -7 at 1. 8)