CMS Tracker FED Back End FPGA 12 FrameSyncout

CMS Tracker FED Back End FPGA 12 Frame_Sync_out 0 Frame_Sync_In 0 Readout_Sync_out 0 Readout_Sync_In 0 Monitor_out 0 Monitor_In 0 Config_out 0 4 Reset TTCrx FE 0 TTS Frame_Sync_out 7 Frame_Sync_In 7 Readout_Sync_out 7 Readout_Sync_In 7 SLINK 4 Data_stream 7 8 Clock 40 Full flags 3 Bank Voltages Core Voltage Rutherford Appleton Laboratory Instrumentation Department 64 SLINK 64 ~64 K J 0 J 2 7 pairs 32 + 13 pairs ADDR/CNTRL FE 7 Monitor_Sync_out 7 Monitor_Sync_In 7 LVDS ef, pf & ff VME Internal Data_stream 0 Single ended DCI LVDS pair option 12 Clock 40 QDR SSRAM 18 DATA IN x 2 QDR Common Address 18 DATA OUT Bank DCI Resistors 2 Temp Flags ‘I 2 C’ LM 82 Temp Sense diode BSCAN Electronic System Design Group Rob Halsall et al. 21 October 2002

CMS Tracker FED Back End FPGA Clock 40 in 1 Clock 40 out 8 16 16 8 ‘VME’ DDR DCMs x 1 x 2 x 4 Channel Link 3 x 8 Frame_Syncs Readout_Syncs Load_monitor SLINK/Channel Link Header Data 8 x Lengths, Pointers Fill/run/freeze FF, PF, busy 1 Reset 3 Control In Out Control x 8 8 x DECODE CONTROL & MONITOR 18 QDR SSRAM x 2/x 4 burst 40 Mhz 9 TTC Rx R/W Address Generator Reset Control Data TTS Data Out 320 MHz 2 FF/PF Flags 20 80/160 MHz Address 4 DDR Data_stream 7 640 MHz LVDS 8 x 8 Spare Data_stream 0 64 64 4 18 80 MHz Data In 320 MHz 160 MHz Rutherford Appleton Laboratory Instrumentation Department Electronic System Design Group Rob Halsall et al. 21 October 2002

FS in 0. . 7 FS out 0. . 7 RS in 0. . 7 RS out 0. . 7 Load 0. . 7 Frame Sync Interface Readout Sync Interface Monitor 0. . 7 Load/Monitor Interface Data tap 0. . X Header Generation SLINK Data 0. . 63 SLINK-VME TTC 0. . 9 Header VME Interface Control Address Data Control VME Back End Control Block Address Generator Data Header Data TTC Interface Event Scalers FE FPGA FF/PF 0. . 1 TTS 0. . X SLINK CTRL 0. . X Reset Rutherford Appleton Laboratory Instrumentation Department Flow Control Interface Electronic System Design Group Address Generator Control Rob Halsall et al. 21 October 2002

Frame Sync FS in 0. . 7 FIFO 1 K Serial Detect Compare CTRL BUS fs_strobe, status= good, some header errors, arrival time error, fatal error reset, freeze HEADER BUS fs_fifo_empty, fs_fifo_full, fifo_data=median header+status 8 x Serial Data, markers & control data DPM 1 K circular buffer Rutherford Appleton Laboratory Instrumentation Department VME BUS Electronic System Design Group Rob Halsall et al. 21 October 2002

Readout Sync CTRL BUS RS in 0. . 7 rs_strobe, status= good, arrival time error, fatal error reset, freeze, readout_next RS out 0. . 7 FIFO 1 K Serial Detect Address Gen Total_length_fifo_empty, total_length_fifo_full, fifo_data= total length FIFO 8 K fifo_data= 8 x sub_lengths FIFO 8 K fifo_data= 8 x pointer_offsets FIFO 8 K HEADER BUS copy_fifo_empty, copy_fifo_full, fifo_data= sub_lengths 8 x Serial Data, markers & control data DPM 1 K circular buffer Rutherford Appleton Laboratory Instrumentation Department VME BUS Electronic System Design Group Rob Halsall et al. 21 October 2002

Load/Monitor DPM 1 K Config in 0. . 7 Config out 0. . 7 Serial I/O Engine Output ‘VME’ BUS DPM 1 K Input DPM 1 K Monitor in 0. . 7 Monitor out 0. . 7 Serial I/O Engine Output ‘VME’ BUS DPM 1 K Input Rutherford Appleton Laboratory Instrumentation Department Electronic System Design Group Rob Halsall et al. 21 October 2002

SLINK-VME CTRL BUS QDR/SLINK Interface DPM 1 K VME-SLINK Readout ‘VME’ BUS FIFO 1 K QDR Event Data moved in blocks into DPM Burst transfer over VME Wait on software handshake before continuing Double buffered Rutherford Appleton Laboratory Instrumentation Department Electronic System Design Group Rob Halsall et al. 21 October 2002

TTC Interface CTRL BUS TTC 0. . 9 ttc_strobe reset, freeze Bx, Ex FIFO 1 K TTC Interface Em Hdr Header FIFO 1 K DPM 1 K VME Rutherford Appleton Laboratory Instrumentation Department Electronic System Design Group Rob Halsall et al. 21 October 2002

Flow Control core VME soft reset Addr Gen FIFO FF Internal Freeze Latch FE FPGA FF Addr Gen FIFO PF Internal FIFO PF TTS BUSY FE FPGA PF Addr GEN FF Internal FIFO EF Internal Freeze Addr GEN Controls RS Controls Fill Flow Control Fill event SLINK CTRL Busy Addr GEN EF Addr GEN Busy Internal Freeze Simplest flow control; Empty Flow Control Halt on any buffer full Busy on any buffer partially full Readout event Diagnostic Event Logger Circular Buffers VME Time stamped Control Registers Rutherford Appleton Laboratory Instrumentation Department Electronic System Design Group Rob Halsall et al. 21 October 2002

CMS Tracker FED System Timing Frame Sync In 256+12 #2234 ADC Output Header Data Frame Sync Median header+ Status Message Frame Sync Out Accept/abort Handshake Message Frame Sync In #2233 Readout Sync Out Processed Message Readout Sync In #2220 Next/delete #2221 Readout Message #2219 Data Length #2220 Data Burst #2221 Data Burst NB Frame Sync In - Abort/Accept not used, auto accepts. Readout Sync In - delete not used. Rutherford Appleton Laboratory Instrumentation Department Electronic System Design Group Rob Halsall et al. 21 October 2002

CMS Tracker FED Back End FPGA #FFFFF Event N+1 Write Ptr 7 FE 7 Write Ptr 2 Event N Write Ptr 2 Write Ptr 1 Write Ptr 0 Header Ptr FE 1 Write Ptr 1 FE 0 Write Ptr 0 Read Ptr Event N-1 Read Ptr #00000 T 0 Rutherford Appleton Laboratory T 1 Instrumentation Department Electronic System Design Group T 2 Rob Halsall et al. 21 October 2002

CMS Tracker FED - Back End FPGA Floorplan Die Package SLINK FE_FPGA_Inputs VME QDR Same frame 456 & 676 ? Clocks Rutherford Appleton Laboratory Instrumentation Department XC 2 V 1000 FG 456 - 324 I/O XC 2 V 1500 FG 676 - 396 I/O XC 2 V 2000 FG 676 - 456 I/O XC 2 V 3000 FG 676 - 484 I/O Electronic System Design Group Rob Halsall et al. 21 October 2002