CMS ECAL A new readout system architecture for

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CMS ECAL A new readout system architecture for the CMS ECAL Magnus Hansen 20030930

CMS ECAL A new readout system architecture for the CMS ECAL Magnus Hansen 20030930

Agenda l l l l Short history r. Evolution A new readout system architecture

Agenda l l l l Short history r. Evolution A new readout system architecture A New ASIC: FENIX Front End Card System Test Conclusion LECC 2003 September 30 th 2003 M. Hansen, CERN. magnus. hansen@cern. ch

Agenda l l l l Short history r. Evolution A new readout system architecture

Agenda l l l l Short history r. Evolution A new readout system architecture A New ASIC: FENIX Front End Card System Test Conclusion New System Architecture Chips / ASICs Electronics Modules System LECC 2003 September 30 th 2003 M. Hansen, CERN. magnus. hansen@cern. ch

Old Design Architectural Overview TTC Local Triggers In Stand alone Mode Regional Trigger Data

Old Design Architectural Overview TTC Local Triggers In Stand alone Mode Regional Trigger Data TTS Partition ROSE DCC DAQ Data FE LECC 2003 September 30 th 2003 M. Hansen, CERN. magnus. hansen@cern. ch

r. Evolution l Simple Front End s l Large number of optical link s

r. Evolution l Simple Front End s l Large number of optical link s l 1 link per channel Large upper level readout system s l Minimal hardware Maximal flexibility (FPGA tech. ) Estimated not to be affordable l Developed Front End s s l Modest number of optical link s l l LECC 2003 September 30 th 2003 M. Hansen, CERN. Trigger Primitive generation Primary event storage 2 data links per tower (25 ch) Modest upper level readout system Estimated to be affordable magnus. hansen@cern. ch

New architecture l Implemented in Front End s s l MGPA + Multi-ADC for

New architecture l Implemented in Front End s s l MGPA + Multi-ADC for dynamic range compression and digitization (Change from analogue gain switching to digital gain selection) TPG (Trigger Primitive Generator) Pipeline storing digitized data waiting for level 1 trigger decision Primary event buffer Implemented in Counting room s s CCS (Clock and Control System card, Collaboration with CMS Tracker, Pixel) DCC (Data Concentrator Card) TCC (Trigger Concentrator Card) SRP (Selective Readout Processor) LECC 2003 September 30 th 2003 M. Hansen, CERN. magnus. hansen@cern. ch

Architectural Overview TTC Local Triggers In Stand alone Mode TTS Partition CCS Regional Trigger

Architectural Overview TTC Local Triggers In Stand alone Mode TTS Partition CCS Regional Trigger Data TCC Trigger Data FE DAQ Data DCC DAQ Data SRP LECC 2003 September 30 th 2003 M. Hansen, CERN. magnus. hansen@cern. ch

Front End System Functional Requirements l Trigger Primitive Generation s s Absolute calibration of

Front End System Functional Requirements l Trigger Primitive Generation s s Absolute calibration of each channel Implement existing well defined algorithm Verification needed before production è No future basic changes possible è s l Latency budget imposed Readout of data corresponding to positive trigger decision s Dead time free è s Three clocks / trigger imposed by TTC system 100 k. Hz level 1 trigger rate Some trigger rules apply è Overflow protection è s Programmable level 1 trigger delay è l Pipeline of programmable length Support for monitoring s Laser monitoring, temperature measurements, etc. LECC 2003 September 30 th 2003 M. Hansen, CERN. magnus. hansen@cern. ch

Other Requirements and Constraints l Debugging and testability features s Pattern injection è s

Other Requirements and Constraints l Debugging and testability features s Pattern injection è s s Boundary scan / scan chains BIST è l l Built In Self Test for production test and in situ Radiation environment Size s l Possibility to inject known pattern in the beginning of the trigger primitive generation and the readout chain Have to fit behind served crystals Short development time s s s Start June 2002 Full production January 2004 One advantage – knowledge of the requirements LECC 2003 September 30 th 2003 M. Hansen, CERN. magnus. hansen@cern. ch

The Front End - A Readout Cube l Motherboard s s l VFE card

The Front End - A Readout Cube l Motherboard s s l VFE card s s l Analogue Signal Processing Digitization LVR card s l Creating flat surface for electronics installation Kapton cable to APD connector Voltage regulation for FE system FE card s Digital Signal Processing è s Temporary storage è l Trigger Primitive generation Pipeline, event buffer GOH s Complete Optical transmitter module including a GOL and a laser diode LECC 2003 September 30 th 2003 M. Hansen, CERN. magnus. hansen@cern. ch

A technical choice i) l l Single Front End ASIC O(500) IOs s s

A technical choice i) l l Single Front End ASIC O(500) IOs s s l l Huge chip ~20 by 20 mm O(4000) chips in CMS ECAL Quickly considered as a non-optimal choice LECC 2003 September 30 th 2003 M. Hansen, CERN. magnus. hansen@cern. ch

A technical choice ii) l l l Seven Front End ASICs Three types O(150)

A technical choice ii) l l l Seven Front End ASICs Three types O(150) IOs each s l l ~7 by 7 mm O(20000) + O(4000) chips in CMS ECAL Soon considered as a nonoptimal choice LECC 2003 September 30 th 2003 M. Hansen, CERN. magnus. hansen@cern. ch

The technical choice l l Seven Front End ASICs Single type Three operation modes

The technical choice l l Seven Front End ASICs Single type Three operation modes O(150) IOs s l l l ~7 by 7 mm O(30000) chips in CMS ECAL Considered as an optimal choice The new ASIC is called FENIX s Front End New Intermediate data e. Xtractor LECC 2003 September 30 th 2003 M. Hansen, CERN. magnus. hansen@cern. ch

FENIX Description 1: Four Operation Modes l Strip s s l TCP s s

FENIX Description 1: Four Operation Modes l Strip s s l TCP s s l Trigger Cell Processor Finalising the trigger primitive for one trigger tower in the Barrel DAQ s s l Creating filtered Strip / Pseudo-strip sums for TCP inputs Pipelines and primary event buffers Tower (Super Crystal) readout state machine Event encapsulation MEM s s Reading out the Laser monitoring system Pipelines and primary event buffers LECC 2003 September 30 th 2003 M. Hansen, CERN. magnus. hansen@cern. ch

FENIX Description 2: Control l Fast control s l T 1 signal as defined

FENIX Description 2: Control l Fast control s l T 1 signal as defined in the Tracker slow control system Slow Control s I 2 C interface è “ 100” => Level 1 Trigger accept è “ 101” => BC 0 ø Standard protocol ø Direct addressing of all set-up addresses è ø Local Bunch Crossing counter reset è Compatible with CCU I 2 C master ports è Fully synchronous design è “ 110” => Re-synch ø Reset of all counters and state machines è è “ 110110” => Power-up reset ø Reset of all counters and state machines and load default values into all registers è ø Synthesizable ø Auto P&R “ 111” => Force VFE mode ø From programmable default mode to programmable calibration mode Extended 10 bit addressing s 150 set-up addresses 132 Set-up registers è 18 RAM access è “ 1100110” => Power-up reset ø As above LECC 2003 September 30 th 2003 M. Hansen, CERN. magnus. hansen@cern. ch

Development Acceleration l Intermediate device s s s l Xilinx FPGA Cadence for simulation

Development Acceleration l Intermediate device s s s l Xilinx FPGA Cadence for simulation Synplify for synthesis Modern ASIC design tools s Synopsis for synthesis Silicon Ensemble for Place & Route Very short design turnaround time è l 2 weeks claimed Generic HDL description s No component instantiation LECC 2003 September 30 th 2003 M. Hansen, CERN. magnus. hansen@cern. ch

ASIC Emulation in FPGA l Features s l Observable functionality identical Identical footprint Identical

ASIC Emulation in FPGA l Features s l Observable functionality identical Identical footprint Identical pin-out Not implemented to save resources s Triple-redundancy in registers Error Correcting Code in RAMs BIST in RAMs LECC 2003 September 30 th 2003 M. Hansen, CERN. magnus. hansen@cern. ch

ASIC Emulation in FPGA - Applied HDL design rules l Generic Source Code s

ASIC Emulation in FPGA - Applied HDL design rules l Generic Source Code s l Exception: RAM s l No process dependent component instantiation Technology specific, recommended not to infer Adopted strategy: s All functional simulation done with generic RAM è “Superset” s For the FPGA, the Xilinx RAM block is wrapped and instantiated è Routed s of Xilinx RAM and ASIC RAM used design simulated and verified for conformity For the ASIC, the modular static RAM cell developed at CERN is wrapped and instantiated è Routed LECC 2003 September 30 th 2003 design simulated and verified for conformity M. Hansen, CERN. magnus. hansen@cern. ch

FENIX ASIC Radiation Tolerance: Strategy l Observation s s l Strategy s s l

FENIX ASIC Radiation Tolerance: Strategy l Observation s s l Strategy s s l ASIC technology is radiation tolerant Registers and RAM cells subject to SEU Protect against SEU Not protect against hardware failure Testability s s Always a challenge Improved by insertion of a “testability flag” LECC 2003 September 30 th 2003 M. Hansen, CERN. magnus. hansen@cern. ch

FENIX ASIC SEU Tolerance 1: Set-up Registers l Set-up registers s Triple-redundant flip-flops è

FENIX ASIC SEU Tolerance 1: Set-up Registers l Set-up registers s Triple-redundant flip-flops è SEU resistant ø Voting logic ø three (two) clocks long write pulse needed s Features è Synthesizable s Test è Any discrepancy flagged è Discrepancy when written LECC 2003 September 30 th 2003 M. Hansen, CERN. magnus. hansen@cern. ch

Triple-redundant Set-up register VHDL code setup_register : process (clock 40) begin if rising_edge(clock 40)then

Triple-redundant Set-up register VHDL code setup_register : process (clock 40) begin if rising_edge(clock 40)then if pwup_reset = '0' then register 1_8 b <= pwup_value; seu_flag <= '0'; elsif address = register_address and write_enable = '1' then register 1_8 b <= write_data; else register 1_8 b <= voted_register_value_8 b; end if; register 3_8 b <= register 2_8 b; register 2_8 b <= register 1_8 b; if register 1_8 b = register 2_8 b and register 1_8 b = register 3_8 b then seu_flag <= '0'; else seu_flag <= '1'; end if; else null; end if; end process setup_register; LECC 2003 September 30 th 2003 M. Hansen, CERN. magnus. hansen@cern. ch

FENIX ASIC SEU Tolerance 2: State Machine l State Machine s Triple-redundant è SEU

FENIX ASIC SEU Tolerance 2: State Machine l State Machine s Triple-redundant è SEU resistant ø Voting logic ø Except state changes s Features è Synthesizable s Test è Any discrepancy flagged è Discrepancy when state change LECC 2003 September 30 th 2003 M. Hansen, CERN. magnus. hansen@cern. ch

FENIX ASIC SEU Tolerance 3: RAM l RAM s Hamming code è Encode at

FENIX ASIC SEU Tolerance 3: RAM l RAM s Hamming code è Encode at write è Decode & Correct at read ø one bit error correction s Features è Synthesizable è Single s bit SEU safe Test è ECC Decoder ø During BIST execution è ECC Encoder ø During normal operation ø Through slow control (I 2 C) LECC 2003 September 30 th 2003 M. Hansen, CERN. magnus. hansen@cern. ch

FENIX ASIC Testability l Test time budget: 1 second s l Without chip handling

FENIX ASIC Testability l Test time budget: 1 second s l Without chip handling Triple-redundant Registers s Testability flag can be used as a signature of operation l RAM BIST s s s Fully automatic Write whole RAM and read back Launched by a pulse on IO pin Boundary scan è Tester è s Observable on external pins Boundary scan è Tester è s LECC 2003 September 30 th 2003 M. Hansen, CERN. Can be launched and monitored in situ (I 2 C) magnus. hansen@cern. ch

FENIX ASIC Status and Plans l First submitted February 2003 s s Received back

FENIX ASIC Status and Plans l First submitted February 2003 s s Received back from foundry in May Not yet received back from packaging è l Becoming critical Next submission after ESR s s 9 th of October Engineering run Final design è O(3000) dies, for up to 3 CMS ECAL Super Modules è s l Tested chips back before end 2003 Production s Beginning of 2004 LECC 2003 September 30 th 2003 M. Hansen, CERN. magnus. hansen@cern. ch

FE Card Functionality and Performance l Full TPG in Barrel s s s Sum

FE Card Functionality and Performance l Full TPG in Barrel s s s Sum of Five filtered strip sums Single data link to TCC and regional trigger 11 clocks latency è l Partial TPG in End Cap s s s Five filtered strip sums Five data links to TCC and regional trigger 7 clocks latency è l FE card input to GOH connector Readout s s s Serves 25 channels Single data link to DCC and DAQ Dead time free 7. 2 us service time, 25 primary event buffers, (10 samp/ch/evt, P(n=d) = 10 -8*) è Null event insertion up to 127 pending events è s Programmable pipeline length corresponding to level 1 trigger delay *TTS for CMS DAQ, A. Racz LECC 2003 September 30 th 2003 M. Hansen, CERN. magnus. hansen@cern. ch

FE card Layout LECC 2003 September 30 th 2003 M. Hansen, CERN. magnus. hansen@cern.

FE card Layout LECC 2003 September 30 th 2003 M. Hansen, CERN. magnus. hansen@cern. ch

Tower in Super Module Trigger GOH QPLL VFE CCU Readout GOH FENIX FPGA LVR

Tower in Super Module Trigger GOH QPLL VFE CCU Readout GOH FENIX FPGA LVR LECC 2003 September 30 th 2003 M. Hansen, CERN. magnus. hansen@cern. ch

Beam Test 2003 LECC 2003 September 30 th 2003 M. Hansen, CERN. magnus. hansen@cern.

Beam Test 2003 LECC 2003 September 30 th 2003 M. Hansen, CERN. magnus. hansen@cern. ch

Conclusion l l A New Readout System Architecture for CMS ECAL has been presented

Conclusion l l A New Readout System Architecture for CMS ECAL has been presented The CMS ECAL Front End Card s Serving 25 readout channels è Tower in the Barrel è Super-Crystal in the End Cap l The FENIX chip s s l Implements the main functionality on the Front End card Three (four) operation modes FPGA emulator implemented ASIC prototype implemented, Final design submitted after ESR Prototype system successfully tested in beam LECC 2003 September 30 th 2003 M. Hansen, CERN. magnus. hansen@cern. ch