CMPUT 680 Fall 2003 Topic B Open Research

CMPUT 680 - Fall 2003 Topic B: Open Research Compiler José Nelson Amaral http: //www. cs. ualberta. ca/~amaral/courses/680 CMPUT 680 - Compiler Design and Optimization 1

Logical Compilation Model driver (sgicc/sgif 90/sgi. CC) back end (be) front end + IPA (gfec/gfecc/mfef 90) Src (. c/. C/. f) WHIRL (. B/. I) linker (ld) obj (. o) Data Path CMPUT 680 - Compiler Design and Optimization a. out/. so Fork and Exec 2

Components of Pro 64 Front end Interprocedural Analysis and Optimization Loop Nest Optimization and Parallelization Global Optimization Code Generation CMPUT 680 - Compiler Design and Optimization 3

Data Flow Relationship Between Modules Lower to High W. -IPA. B Local IPA Main IPA -O 3 LNO Inliner gfec . I gfecc lower I/O (only for f 90) f 90 Take either path Very high WHIRL High WHIRL Mid WHIRL Low WHIRL -O 0 -phase: w=off -O 2/O 3 WHIRL C . w 2 c. c. w 2 c. h WHIRL fortran . w 2 f. f Lower all Lower Mid W CMPUT 680 - Compiler Design and Optimization CG Main opt 4

Front Ends z. C front end based on gcc z. C++ front end based on g++ z. Fortran 90/95 front end from MIPSpro CMPUT 680 - Compiler Design and Optimization 5

Intermediate Representation IR is called WHIRL z Common interface between components z Multiple languages and multiple targets z Same IR, 5 levels of representation z Continuous lowering as compilation progresses z Optimization strategy tied to level CMPUT 680 - Compiler Design and Optimization 6

IPA Main Stage Analysis yalias analysis yarray section ycode layout Optimization (fully integrated) yinlining ycloning ydead function and variable elimination yconstant propagation CMPUT 680 - Compiler Design and Optimization 7

IPA Design Features z. User transparent z. Provide info (e. g. alias analysis, procedure properties) smoothly to: yloop nest optimizer ymain optimizer ycode generator CMPUT 680 - Compiler Design and Optimization 8

Loop Nest Optimizer/Parallelizer z. All languages (including Open. MP) z. Loop level dependence analysis z. Uniprocessor loop level transformations z. Automatic parallelization CMPUT 680 - Compiler Design and Optimization 9

Loop Level Transformations z Based on unified cost model z Heuristics integrated with software pipelining y. Loop Fission y. Loop Fusion y. Loop Unroll and jam y. Loop interchange y. Loop Peeling y. Loop Tiling y. Vector data prefetching CMPUT 680 - Compiler Design and Optimization 10

Parallelization z. Automatic Array privatization Doacross parallelization Array section analysis z. Directive based Open. MP Integrated with automatic methods CMPUT 680 - Compiler Design and Optimization 11

Global Optimization Phase z Use only SSA as program representation z SSA is unifying technology z Implements all traditional global optimizations z Every optimization preserves SSA form z Can reapply each optimization on asneeded basis CMPUT 680 - Compiler Design and Optimization 12

Pro 64 Extensions to SSA z. Representing aliases and indirect memory operations z. Integrated partial redundancy elimination (SSA PRE) z. Support for speculative code motion z. Register promotion via load and store placement CMPUT 680 - Compiler Design and Optimization 13

Feedback Used throughout the compiler z Instrumentation can be added at any stage z Explicit instrumentation data incorporated where inserted z Instrumentation data maintained and checked for consistency through program transformations. CMPUT 680 - Compiler Design and Optimization 14

Design for Debugability (DFD) and Testability (DFT) z DFD and DFT build-in from start z Can build with extra validity checks z Simple option specification used to: y. Substitute components known to be good y. Enable/disable full components or specific optimizations y. Invoke alternative heuristics y. Trace individual phases CMPUT 680 - Compiler Design and Optimization 15