CMOS Factory ROCHESTER INSTITUTE OF TECHNOLOGY MICROELECTRONIC ENGINEERING

CMOS Factory ROCHESTER INSTITUTE OF TECHNOLOGY MICROELECTRONIC ENGINEERING CMOS Factory Laboratory Dr. Lynn Fuller Webpage: http: //people. rit. edu/lffeee Microelectronic Engineering Rochester Institute of Technology 82 Lomb Memorial Drive Rochester, NY 14623 -5604 Tel (585) 475 -2035 Fax (585) 475 -5041 Email: Lynn. Fuller@rit. edu Micro. E Webpage: www. microe. rit. edu Rochester Institute of Technology Microelectronic Engineering 8 -17 -2014 © August 17, 2014, Dr. Lynn Fuller, Professor CMOS_Factory. ppt Page 1

CMOS Factory INTRODUCTION This document contains items that should be included in the students lab notebook. This includes general information about the processes and products made in the student factory. Rochester Institute of Technology Microelectronic Engineering © August 17, 2014, Dr. Lynn Fuller, Professor Page 2

CMOS Factory INTRODUCTION RIT is supporting two different CMOS process technologies. The older p-well CMOS and SMFL-CMOS have been phased out. The SUB-CMOS process is used for standard 3 Volt Digital and Analog integrated circuits. This is the technology of choice for teaching circuit design and fabricating CMOS circuits at RIT. The ADVCMOS process is intended to introduce our students to process technology that is close to industry state-of-the-art. This process is used to build test structures and develop new technologies at RIT p-well CMOS RIT SMFL-CMOS RIT Subµ-CMOS RIT Advanced-CMOS l = 4 µm l = 1 µm l = 0. 5 µm l = 0. 25 µm Lmin = 8 µm Lmin = 2 µm Lmin = 1. 0 µm Lmin = 0. 5 µm Rochester Institute of Technology Microelectronic Engineering © August 17, 2014, Dr. Lynn Fuller, Professor Page 3

CMOS Factory RIT SUBµ CMOS RIT Subµ CMOS 150 mm wafers Nsub = 1 E 15 cm-3 Nn-well = 3 E 16 cm-3 Xj = 2. 5 µm Np-well = 1 E 16 cm-3 Xj = 3. 0 µm LOCOS Field Ox = 6000 Å Xox = 150 Å Lmin= 1. 0 µm LDD/Side Wall Spacers 2 Layers Aluminum Rochester Institute of Technology Microelectronic Engineering L Long Channel Behavior 3 Volt Technology VT’s = +/- 0. 75 Volt Robust Process (always works) Fully Characterized (SPICE) © August 17, 2014, Dr. Lynn Fuller, Professor Page 4

CMOS Factory RIT SUBµ CMOS NMOSFET N+ Poly PMOSFET 0. 75 µm Aluminum 6000 Å Field Oxide p+ well contact N+ D/S LDD P-well LDD P+ D/S N-well Channel Stop P-type Substrate 10 ohm-cm Rochester Institute of Technology Microelectronic Engineering © August 17, 2014, Dr. Lynn Fuller, Professor Page 5 n+ well contact

CMOS Factory SUB-CMOS 150 PROCESS SUB-CMOS Versions 150 1. CL 01 2. OX 05 --- pad oxide, Tube 4 3. CV 02 - Si 3 N 4 -1500Å 4. PH 03 – 1 - JG nwell 5. ET 29 – Nitride Etch 6. IM 01 – n-well 7. ET 07 – Resist Strip 8. CL 01 9. OX 04 – well oxide, Tube 1 10. ET 19 – Hot Phos Si 3 N 4 11. IM 01 – p-well 12. OX 06 – well drive, Tube 1 13. ET 06 - Oxide Etch 14. CL 01 15. OX 05 – pad oxide, Tube 4 16. CV 02 – Si 3 N 4 -1500 Å 17. PH 03 – 2 – JG Active 18. ET 29 – Nitride Etch 19. ET 07 – Resist Strip 20. PH 03 - -Pwell Stop 21. IM 01 - stop 22. ET 07 Resist Strip 23. CL 01 24. OX 04 – field, Tube 1 25. ET 19 – Hot Phos Si 3 N 4 26. ET 06 – Oxide Etch 27. OX 04 – Kooi, Tube 1 28. IM 01 – Blanket Vt 29. PH 03 – 4 -PMOS Vt Adjust 30. IM 01 - Vt 31. ET 07 – Resist Strip 32. ET 06 – Oxide Etch 33. CL 01 34. OX 06 – gate, Tube 4 35. CV 01 – Poly 5000 A 36. IM 01 - dope poly 37. OX 08 – Anneal, Tube 3 38. DE 01 – 4 pt Probe 39. PH 03 -5 -JG poly 40. ET 08 – Poly Etch 41. ET 07 – Resist Strip 42. PH 03 – 6 - n-LDD 43. IM 01 44. ET 07 – Resist Strip 45. PH 03 – 7 - p-LDD 46. IM 01 47. ET 07 – Resist Strip 48. CL 01 49. CV 03 –TEOS, 5000 A 50. ET 10 - Spacer Etch 51. PH 03 – 8 - N+D/S 52. IM 01 – N+D/S 53. ET 07 – Resist Strip 54. PH 03 – 9 P+ D/S 55. IM 01 – P+ D/S 56. ET 07 – Resist Strip 57. CL 01 Special - No HF Dip 58. OX 08 – DS Anneal, Tube 2 59. CV 03 – TEOS, 4000 A 60. PH 03 – 10 CC 61. ET 26 - CC Etch 62. ET 07 – Resist Strip 63. CL 01 Special - Two HF Dips 64. ME 01 – Metal 1 Dep 65. PH 03 -11 - metal 66. ET 15 – plasma Etch Al 67. ET 07 Resist Strip 68. SI 01 - Sinter 69. CV 03 – TEOS- 4000Å 70. PH 03 – VIA 71. ET 26 – Via Etch 72. ET 07 – Resist Strop 73. ME 01 – Metal 2 Dep 74. PH 03 - M 2 75. ET 15 – plasma Etch Al 76. ET 07 - Resist Strip 77. SEM 1 78. TE 01 79. TE 02 80. TE 03 81. TE 04 Rochester Institute of Technology Microelectronic Engineering © August 17, 2014, Dr. Lynn Fuller, Professor 2 -6 -13 Page 6

CMOS Factory ASML 5500/200 NA = 0. 48 to 0. 60 variable s= 0. 35 to 0. 85 variable With Variable Kohler, or Variable Annular illumination Resolution = K 1 l/NA = ~ 0. 35µm for NA=0. 6, s =0. 85 Depth of Focus = k 2 l/(NA)2 of Technology = > 1. 0 µm. Rochester for Institute NA = 0. 6 Microelectronic Engineering i-Line Stepper l = 365 nm 22 x 27 mm Field Size © August 17, 2014, Dr. Lynn Fuller, Professor Page 7

RIT SUB-CMOS PROCESS NMOSFET N+ Poly PMOSFET LVL 6 – P-LDD 0. 75 µm Aluminum LVL 1 – n-WELL 6000 Å Field Oxide p+ well N+ D/S LDD contact P-well N-well LDDP+ D/S n+ well contact LVL 7 – N-LDD LVL 2 - ACTIVE Channel Stop P-type Substrate 10 ohm-cm LVL 8 - P+ D/S LVL 3 - STOP POLY CC ACTIVE P SELECT LVL 9 - N+ D/S LVL 4 - PMOS VT METAL N SELECT LVL 10 - CC LVL 5 - POLY N-WELL 11 PHOTO LEVELS LVL 11 - METAL

CMOS Factory ASML MASK Chrome Side Mirrored 90° Chip Bottom at Bottom Rochester Institute of Technology Microelectronic Engineering Non Chrome Side As loaded into Reticle Pod, Chrome Down, Reticle Pre. Alignment Stars Sticking out of Pod © August 17, 2014, Dr. Lynn Fuller, Professor Page 9

CMOS Factory RIT ADVANCED CMOS RIT Advanced CMOS 150 mm Wafers Nsub = 1 E 15 cm-3 or 10 ohm-cm, n or p Nn-well = 1 E 17 cm-3 L Xj = 2. 5 µm Np-well = 1 E 17 cm-3 Xj = 2. 5 µm Shallow Trench Isolation Field Ox = 4000 Å Long Dual Doped Gate n+ and p+ Channel Xox = 100 Å Behavior Lmin= 0. 5 µm LDD/Nitride Side Wall Spacers Ti. Si 2 Silicide Tungsten Plugs, CMP, 2 Layers Aluminum Rochester Institute of Technology Microelectronic Engineering © August 17, 2014, Dr. Lynn Fuller, Professor Page 10

CMOS Factory RIT ADVANCED CMOS NMOSFET PMOSFET N+ Poly p+ well contact P+ Poly N+ D/S P+ D/S LDD P-well N-well LDD Rochester Institute of Technology Microelectronic Engineering © August 17, 2014, Dr. Lynn Fuller, Professor Page 11 n+ well contact

CMOS Factory ADV-CMOS 150 PROCESS ADV-CMOS Versions 150, Two level Metal 21. PH 03 – level 5 – PMOS VT adjust 41. CV 02 – nitride spacer dep 42. ET 39 – sidewall spacer etch 1. OX 05 --- pad oxide 500 Å, Tube 4 22. IM 01 – 1. 75 E 12, B 11, 60 Ke. V 23. ET 07 – ash 43. PH 03 – level 9 - N+D/S 2. CV 02 - 1500 Å Si 3 N 4 Deposition 24. ET 06 – etch 500 Å pad oxide 44. IM 01 – 4 E 15, P 31, 60 Ke. V 3. PH 03 – level 1 - STI 25. CL 01 – pre-gate oxide RCA clean 45. ET 07 – ash 4. ET 29 - etch Nitride 26. ET 06 – etch native oxide 46. PH 03 – level 10 - P+ D/S 5. ET 07 – ash 27. OX 06 – 100 Å gate oxide, Tube 4 47. IM 01 – 4 E 15, B 11, 50 Ke. V 6. CL 01 – RCA clean 28. CV 01 – poly deposition, 4000 Å 48. ET 07 – ash 7. OX 04 – First Oxide Tube 1 29. PH 03 – level 6 – poly gate 49. CL 01 – RCA clean 8. ET 06 – Etch Oxide nd 30. ET 08 – poly gate plasma etch 50. OX 08 – DS Anneal, Tube 2, 3 9. OX 04 – 2 Oxide Tube 1 31. ET 07 – ash 51. ET 06 – Silicide pad ox etch 10. PH 03 – level 2 N-Well 32. CL 01 – RCA clean 52. ME 03 – HF dip & Ti Sputter 11. IM 01 – 3 E 13, P 31, 170 Ke. V 33. OX 05 – poly re-ox, 500 Å, Tube 4 53. RT 01 – RTP 1 min, 650 C 12. ET 07 – ash 34. PH 03 – level 7 - p-LDD 54. ET 11 – Unreacted Ti Etch 13. PH 03 – level 3 – p-well 11 35. IM 01 – 4 E 13, B 11, 50 Ke. V 55. RT 02 – RTP 1 min, 800 C 14. IM 01 – 8 E 13, B , 80 Ke. V 36. ET 07 – ash 56. CV 03 – TEOS, P-5000 15. ET 07 – ash 37. PH 03 – level 8 – n-LDD 57. PH 03 – level 11 - CC 16. ET 19 – Hot Phos 31 38. IM 01 – 4 E 13, P , 60 Ke. V 58. ET 06 – CC etch 17. OX 06 – Well Drive, Tube 1 39. ET 07 – ash 59. ET 07 – ash 18. PH 03 – NMOS Vt 40. CL 01 – RCA clean 60. CL 01 – RCA clean 19. IM 01 – 3 E 12, B 11, 30 Ke. V 20. ET 07 - ash L = 0. 5 m VDD = 3. 0 V Rochester Institute of Technology VTN = 0. 75 V Microelectronic Engineering VTP = - 0. 75 V 61. ME 01 – Aluminum 62. PH 03 – level 12 -metal 63. ET 15 – plasma Al Etch 64. ET 07 – ash 65. CV 03 – TEOS 66. PH 03 – Via 67. ET 26 Via Etch 68. ME 01 Al Deposition 69. PH 03 – Metal 2 70. ET 07 - Ash 72. SI 01 – sinter 73. SEM 1 74. TE 01 75. TE 02 76. TE 03 77. TE 04 (Revision 11 -24 -11) © August 17, 2014, Dr. Lynn Fuller, Professor Page 12

RIT ADVANCED CMOS PROCESS NMOSFET p+ well contact PMOSFET P+ Poly N+ D/S P+ D/S N-well LDD P-well LDD LVL 1 - STI n+ well contact 12 PHOTO LEVELS LVL 7 - PLDD LVL 2 - NWell LVL 8 - NLDD LVL 3 - Pwell LVL 9 – N+D/S POLY CC ACTIVE P SELECT METAL N SELECT LVL 4 - VTP LVL 10 – P+D/S LVL 5 - VTN LVL 11 - CC LVL 6 - POLY LVL 12 – METAL 1 N-WELL

CMOS Factory MASK ORDER CONTINUED 1 2 3 4 Rochester Institute of Technology Microelectronic Engineering © August 17, 2014, Dr. Lynn Fuller, Professor Page 14

CMOS Factory PRODUCTS New John Galt Test Chip (Sub-CMOS and Adv-CMOS) Older Obsolete Chips: Mixed Analog/Digital Test Chip (Sub-CMOS Process) Test Chip (Advanced CMOS Process) John Galt Test Chip (Sub-CMOS Process) 4 -Bit Microprocessor (Sub-CMOS Process) Analog to Digital Converter (Sub-CMOS Process) Rochester Institute of Technology Microelectronic Engineering © August 17, 2014, Dr. Lynn Fuller, Professor Page 15

CMOS Factory JOHN GALT CMOS TESTCHIP 2010 Rochester Institute of Technology Microelectronic Engineering © August 17, 2014, Dr. Lynn Fuller, Professor Page 16

CMOS Factory FACTORY (MULTIDISCIPLINARY) TEAMS Red Group 1. Shrishti 2. Alycia 3. Orange Group 1. Lilah 2. Paige 3. Yellow Group 1. Anthony 2. Jefferson 3. Green Group 1. Michal 2. Richard 3. Blue Group 1. Eric 2. Andrew 3. Every two weeks groups shift discipline (to the right). For example the red group does Diffusion week 1&2, Red does Lithography week 3&4, Red does CVD/Plasma week 5&6, etc. Diffusion Lithography Bruce Furnace AG-RTP Blue M Oven Nanospec Spectromap CDE Resistivity Map Canon Stepper SSI Track CD Linewidth Overlay Branson Asher Discipline PVD/Plasma Etch CVD/PECVD Wet Etch/CMP CVC 601 Drytech Quad Lam 490 Lam 4600 Nanospec Tencore P 2 ASM 6”LPCVD P-5000 Nanospec Spectromap Varian 350 D While in each discipline the students will Process lots requiring steps in that discipline Perform follow up Inspection and Metrology Investigate and Update SPC data Monitor non-device process metrics Rochester Institute of Technology Perform a “pass down” at the end of (2 weeks) Microelectronic Engineering Track lots in and out of Mesa © August 17, 2014, Dr. Lynn Fuller, Professor Page 17 Al Wet Etch BOE Etch RCA Clean Hot Phos Nitride Etch BOE Solvent Strip CMP and CMP Clean Nanospec Surfscan SEM 8 -21 -2013

CMOS Factory EXAMPLE TEAM REPORT AT END OF ROTATION Discipline: Lithography Date: Nov 30 - Dec 8, 2012 Group Members: Matt Mc. Quillan, Dave Pawlik Lot Advancement: F 031013 – CC Photo –Changed Stepper Job to Align using TVPA Marks Only added 2 µm shift to alignment key locations on pg 4/ in process file F 040119 – Resist Strip F 040614 – Active Photo F 031013 – LDDP Photo F 040920 – Resist Strip-Changed Stepper Job to Align using TVPA Marks Only F 040920 – P-Well Photo-Changed Stepper Job to Align using TVPA Marks Only F 030922 - Resist Strip Other: Short Loop Resist Coat Thickness measurement for Coat. rcp, Xpr=1. 0 µm Branson Asher often gives purge timeout error, select continue Rochester Institute of Technology Microelectronic Engineering © August 17, 2014, Dr. Lynn Fuller, Professor Page 18

Rochester Institute of Technology Microelectronic Engineering Dr. Lynn Fuller Red (Diffusion) Orange (Lithography) Yellow (Plasma Etch) Green (Implant/CVD) Blue (wet Etch) Date: 8 -26 -13 Lot Status Report Time: 8: 00 am STEP Next Operation Qty Comments Lot No Product Process / Version Current operation F 111208 JOHN GALT SUB-CMOS 150 PH 03 X 70 ET 26 2 ORANGE F 120825 JOHN GALT SUB-CMOS 150 IM 01 X 46 ET 07 4 YELLOW F 121126 JOHN GALT SUB-CMOS 150 CV 01 X 35 IM 01 2 GREEN F 121208 JOHN GALT SUB-CMOS 150 ET 06 X 26 OX 04 3 BLUE F 130207 JOHN GALT SUB-CMOS 150 OX 04 X 9 ET 19 4 RED, TUBE 1 F 130620 JOHN GALT SUB-CMOS 150 CL 01 X 1 OX 05 3 BLUE F 130626 JOHN GALT ADV-CMOS 150 OX 05 X 1 CV 02 3 RED, TUBE 4 Q P ORANGE – determine correct exposure time for lot numbers using MA 150 contact exposure - prepare wafers for testing aluminum plasma etch - test completed wafers

CMOS Factory OPERATOR FLOW CHART FOR FACTORY WORK START Access MESA Lot Status No No On Hold? In Queue? Yes Yes INITIAL QUALITY CHECK Count Wafers Check Picture Log Book Think Refer to Previous Process Step Check MESA Move-Out Comments Prelininary Quality Check Mesa History Who Did Move-In Do Move-In Start Run Timer Yes Pass ? See Lab Instructor No See Lab Instructor Contact Person Determine What To Do Next No Do Work Follow MESA Instructions Exactly Check Equipment Status Apply Lot Selection Rules Find Wafers Do Photo first Do Oldest Lot Next Separate Lots Current Step Match Skill Level Use Equipment that is Up Find Queue Status Step Number Current Operation Next Operation Quantity On Hold? Continue A LOT SELECTION RULES FINAL QUALITY CHECK Count Wafers Check Picture Log Book Think Do Results Make Sense? Final Quality Check Continue A No See Lab Instructor Pass ? Yes Rochester Institute of Technology Microelectronic Engineering © August 17, 2014, Dr. Lynn Fuller, Professor Stop Run Timer Move Out Record Data Clean Up Return Wafers Return Masks Page 20 END

CMOS Factory SPC CHARTS SPC 6 SC_FO SPC 6 SC_GOX SPC 6 SC_KOX SPC 6 SC_LTO SPC 6 SC_MTL SPC 6 SC_N 1 SPC 6 SC_N 2 SPC 6 SC_PAD SPC 6 SC_POL SPC 6 SC_WO SPC 6 SCPROS Field Oxide Thickness Gate Oxide Thickness Kooi Oxide Thickness LTO/TEOX Oxide Thickness Metal Thickness Nitride Thickness (1500Å) Nitride Thickness (3500Å) Pad Oxide Thickness Poly Thickness Well Oxide Thickness Poly Sheet Resistance Rochester Institute of Technology Microelectronic Engineering © August 17, 2014, Dr. Lynn Fuller, Professor Page 21

CMOS Factory NWA QUALITY ANALYST, SPC CHART Pad Oxide Target 500Å USL 600Å LSL 400Å Mean 535Å Std Dev 25Å Cpk 0. 8648 Cp 1. 332 Rochester Institute of Technology Microelectronic Engineering © August 17, 2014, Dr. Lynn Fuller, Professor Page 22

CMOS Factory SHORT LOOP PROCESS RUNS If no factory lots are available in a specific discipline then group will do short loop process verification runs: BOE – Etch rate verification RTP – Tool operation and recipe verification for Ti. Si and Ti. Si 2 formation PECVD – Tool operation and deposition rate verification for TEOS Oxide and Nitride Resist Coat Thickness Measurement using Spectromap for Coat. rcp and Coat. Mtl. rcp Recipes used by Factory Or SPC Chart verification, evaluation and process capability improvement Verify all MESA picture documents are correct Verify MESA instructions are correct Rochester Institute of Technology Microelectronic Engineering © August 17, 2014, Dr. Lynn Fuller, Professor Page 23

CMOS Factory PROCESS IMPROVEMENT PROJECTS Jorge – CMP Process Improvement Heidi – FT 500 Factory Recipes Keerti – Ti Salicide Process Improvement Murat - Aluminum Deposition in New Flash Evaporator Andrew – Plasma Oxide Etch P-5000 Sam – Fix Mesa Mask ID Check on Move-in Yuan – RTP Gate Oxide Shaoting – Plasma Etch Oxide Drytek Quad Jake – Google Map of John Gault Chip, ETM Mask Paul – High Temperature Oxide STI Process Evaluation Harsha – STI Process Evaluation Xiang – Etch Deep Trenches Kanwal – Theoretical Design of LDD Doping -High Temperature Oxide Rochester Institute of Technology Microelectronic Engineering © August 17, 2014, Dr. Lynn Fuller, Professor Page 24