CMOS Digital Integrated Circuits Lec 9 Super Buffer

CMOS Digital Integrated Circuits Lec 9 Super Buffer Design 1 CMOS Digital Integrated Circuits

Supper Buffer Cload n Given a large capacitance load Cload • How many stages are needed to minimize the delay? • How to size the inverters? Equiv INV 1 1 Cg Cd Cg N 2 Cd 2 Cg 2 Cd N Cg N Cd Cload N: number of inverter stages : optimal stage scale factor 2 CMOS Digital Integrated Circuits

Supper Buffer (Cont. ) where • • • 3 Cg: the input capacitance of the first stage inverter. Cd: the drain capacitance of the first stage inverter. Each inverter is scaled up by a factor of per stage. Cload = N+1 Cg All inverters have identical delay of 0(Cd+ Cg)/(Cd+Cg) which 0 is per gate delay for Equiv INV in ring oscillator circuit with load capacitance = Cg+Cd CMOS Digital Integrated Circuits

Supper Buffer Design Equiv INV 1 1 Cg d Cd Cg d N 2 2 Cd 2 Cg d N Cg N Cd Cload d • Consider N stages, each inverter has same delay 0(Cd+ Cg)/(Cd+Cg). Therefore, 4 CMOS Digital Integrated Circuits

Supper Buffer Design (Cont. ) • Goal: Choose and N to minimize total. » By Cload = N+1 Cg, we have » Plug the above equation into total, we get » To minimize total: 5 CMOS Digital Integrated Circuits

Supper Buffer Design (Con. ) » For the special case Cd=0 ln( opt)=0 opt = e. However, in reality the drain parasitics cannot be ignored. • Example: For Cd=0. 5 f. F, Cg=1 f. F, determine opt and N for Cload = 50 p. F. opt (ln opt -1) = 0. 5 opt = 3. 18 The Super Buffer Design which minimizes total for Cload = 50 p. F is N=7 Equiv INV stages, and opt = 3. 18 6 CMOS Digital Integrated Circuits

CMOS Ring Oscillator Circuit • Oscillation period T is equal to T= PHL 1+ PLH 1+ PHL 2+ PLH 2+ PHL 3+ PLL 3 =2 p+2 p =3· 2 p=6 p • For arbitrary odd number (n) of cascade-connected invertes, we have f=1/T=1/(2·n· p) • Also, we can write p=1/(2·n·f) 1 V 1 Cload, 1 7 2 V 2 Cload, 2 3 V 3 Cload, 3 CMOS Digital Integrated Circuits

Voltage Waveforms of Ring Oscillator Vout VOH V 2 V 1 V 3 V 50% VOL t τPHL 2 τPLH 3 τPHL 1 τPLH 2 τPHL 3 τPLH 1 T 8 CMOS Digital Integrated Circuits