CMOS DIFFERENTIAL AMPLIFIER INTRODUCTION Three problems in singletransistor

CMOS DIFFERENTIAL AMPLIFIER

INTRODUCTION Three problems in single-transistor amplifier stages: Bias and gain sensitive to device parameters (µCox, VT ); sensitivity can be mitigated but often paying price in performance or cost (gain, power, device area, etc. ) l Vulnerable to ground and power-supply noise (in dense IC’s there is cross-talk, 60 Hz coupling, substrate noise, etc. ) l Many signal sources exhibit ”common-mode” drift that gets amplified. l

SOLUTION l Represent signal by difference between two voltages: l Differential ¡ amplifies amplifier: difference between two voltages ¡ rejects components common to both voltages

DIFFERENTIAL AMPLIFIER definitions l Common mode rejection ratio (CMRR) ¡ l Input common-mode range (ICMR) ¡ ¡ l The input common-mode range is the range of common-mode voltages over which the differential amplifier continues to sense and amplify the difference signal with the same gain. Typically, the ICMR is defined by the common-mode voltage range over which all MOSFETs remain in the saturation region. Output offset voltage (VOS(out)) ¡ l CMRR is a measure of how well the differential amplifier rejects the common-mode input voltage in favor of the differential-input voltage. The output offset voltage is the voltage which appears at the output of the differential amplifier when the input terminals are connected together. Input offset voltage (VOS(in) = VOS) ¡ The input offset voltage is equal to the output offset voltage divided by the differential voltage gain.

Why Differential? l One of the most widely used analog block ¡ l High-performance mixed-signal circuits Outline: ¡ ¡ Review of single-ended and differential operation Description of basic differential pair l ¡ Common Mode Rejection Ratio (CMRR) l ¡ ¡ Large signal and small signal analyses Concept, formulation Diff pair with diode-connected and current-source loads Gilbert cell

Single-Ended and Differential Operation l Single-ended ¡ Signal measured with respect to a fixed potential (e. g. gnd) l Differential ¡ Signal measured btwn 2 nodes with equal and opposite signal excursions around a fixed potential (see figure above) ¡ Dotted line -> common-mode level

SE & Diff - discussed Diff circuit more immune to noise l e. g. Power Supply Noise l ¡ Single-Ended: l ¡ Supply varies by DV Vout changes by approx. same amount Differential (symmetric circuit) l l Noise on supply affects VX and VY, not VX-VY (Vout) High-Noise Immunity – rejects common signal (noise)

Advantages of Differential Circuit l 2 adjacent lines ¡ ¡ ¡ one carries small, sensitive signal one carries large clock waveform Capacitive coupling btwn L 1 and L 2 l Transitions on L 2 corrupt signal on L 1 n Sensitive signal distributed as 2 equal magnitude and opposite phases n Clock placed midway, btwn the 2 n Clock transition disturbs differential phases by equal amounts -> difference intacts n Diff output not corrupted -> rejects common-mode noise

Another advantage of diff amp. l In a single CS amplifier, the maximum swing is VDD-(VGS-VTH) l In a differential pair it can be shown that the swing of VX-VY can reach 2[VDD-(VGS-VTH)].

Basic Differential Pair l Amplify diff signal. Mechanism? ¡ ¡ ¡ Concept: incorporate two identical SE signal paths to process the two phases The resulting circuit offers advantages of diff signaling: l e. g. High rejection of supply noise, high output swings, etc. What if input CM level changes? l Bias currents of M 1 and M 2 changes -> vary gm of devices (hence the gain) -> vary output CM level (lowers maximum allowable output swings) Example: If input CM is excessively low (b): l Min values of Vin 1 and Vin 2 may turn off M 1 and M 2 • Lead to severe clipping at output How to solve the problem?

Diff Pair (cont. ) l Add current source ISS ¡ ¡ l Makes ID 1 + ID 2 independent of Vin, CM ID 1=ID 2=ISS/2 when Vin 1=Vin 2, output CM level = VDD-RDISS/2 Main function: ¡ suppress effect of input CM level variations on operation of M 1 and M 2, and output level

Diff Pair – Qualitative Analysis Assume -¥ < Vin 1–Vin 2<¥ l Case 1: Vin 1 more –ve than Vin 2 l ¡ M 1 off, M 2 on -> ID 2=ISS l l l Case 2: As Vin 1 brought closer to Vin 2 ¡ M 1 gradually turns on l l Draws a fraction of ISS from RD 1 (ISS=ID 1+ID 2), lowering Vout 1 Eventually, Vin 1 more +ve than Vin 2 ¡ ¡ ¡ l Vout 1 = VDD Vout 2 = VDD – ISSRD 2 ISS flows through M 1 (on), none through M 2 (off) Vout 2 = VDD Vout 1 = VDD-ISSRD 1 See diagram above for the complete transition

Cont’d … l 2 important characteristics revealed from prev analysis ¡ ¡ Char 1: output’s maximum and minimum levels well-defined (VDD and VDD-RDISS), independent of input CM level Char 2: small-signal gain (slope of Vout 1 -Vout 2 vs. Vin 1 -Vin 2) is maximum for Vin 1=Vin 2 l Gradually falling to zero as |Vin 1 -Vin 2| increases • i. e. circuit becomes more nonlinear as input voltage swing increases • Circuit is in equilibrium when Vin 1=Vin 2

SMALL-SIGNAL DIFFERENTIAL VOLTAGE GAIN l For |ΔVin|≈0 (sufficiently small) we have: where gm is that of a NMOS with a current of ISS/2

Single-ended Differential Voltage Gain

Example What is the required input CM for which RSS sustains 0. 5 V? l Calculate RD for a differential gain of 5 l What happens at the output if the input CM level is 50 m. V higher than the value calculated in (a)? l Let VDD=3 V, (W/L)1=(W/L)2=25/0. 5 l µn. COX=50µA/V 2, VTH=0. 6 V, λ=0, γ=0, RSS=500Ω l

NMOS Differential Amplifiers Small Signal Analysis

Common-Mode Gains We have seen two types of commonmode gain: l AV, CM : Single-ended output due to CM signal. l AV, CM-DM : Differential output due to CM signal. l

Common-Mode Rejection Ratio (CMRR) Definitions In both cases we want CMRR to be as large as possible, and it translates into small matching errors and RSS as large as possible

MOS Loads l (a) Diode-connected load l (b) Current-Source load

MOS Loads: Analysis Method Differential Analysis: Use half-circuit method, with source node at virtual ground. l Common-Mode Analysis: Again use half-circuit method, with appropriate accommodation for parallel transistors, and for RSS. l

MOS Loads: Differential Gain Formulas

Problems with Diode-connected MOS Loads Tradeoff among swing, gain and CM input range: l In order to achieve high gain, (W/L)P must be sufficiently low. Therefore PMOS overdrive voltage must be sufficiently low. As a result CM signal range is reduced. l

Overcoming Diode-connected Load swing problem for higher gains: Use PMOS current sources which reduce gm of diode-connected MOS, instead of lowering (W/L)P of load. Gain can be increased by factor of 5.

Problems with Current-Source MOS Loads l In sub-micron technologies, it’s hard to obtain differential gains higher than 1020.

Solution to low-gain problem: Cascoding

Gilbert Cell l Combine 2 properties of diff pair to develop a versatile building block ¡ ¡ l Small-signal gain of diff pair = f(tail current) 2 transistors in a diff pair provides a means of steering tail current to one of two destinations Variable Gain Amplifier (a) ¡ ¡ Used in a system where signal amplitude may experience large variations and requires inverse changes in gain Vcont defines tail current hence the gain l Max gain = f(voltage headroom limitations, device dimensions)

Cont’d… l 2 diff pairs that continuously vary gain from a –ve to +ve value ¡ Amplify inputs by opposite gains A 1=-gm. RD, A 2=gm. RD, A 1=f(Vcont 1), A 2=f(Vcont 2) l A 1 and A 2 follows the changes in I 1 and I 2 l ¡ How to combine the outputs into a single final output?

Cont’d… l Sum the 2 outputs ¡ l Produce Vout = Vout 1 + Vout 2 = A 1 Vin + A 2 Vin How to realize with transistors? ¡ ¡ Note: Vout 1=RDID 1 -RDID 2 Vout 2=RDID 4 -RDID 3 Vout 1+Vout 2=RD(ID 1+ID 4)-RD(ID 2+ID 3) l l ¡ We don’t add voltages, but add currents by shorting the corresponding drain terminals -> Isum generate output voltage e. g. I 1=0, Vout=gm. RDVin; I 2=0 -> Vout=-gm. RDVin; I 1=I 2 -> gain=0 To change amplifier gain monotonically, I 1 and I 2 must vary in opposite directions l HOW to change amplifier gain/vary the currents in opposite directions?

Cont’d… l Recall diff pair… yes, a diff pair ¡ Observation: l For large |Vcont 11 -Vcont 2| all of tail current steered to one of top diff pair • Gain -> most positive or most negative value l l Redraw the circuit -> GILBERT CELL Note: Vin and Vcont are interchangeable and still works as a VGA