CMOS Circuits 1 Combination and Sequential 2 Static

CMOS Circuits 1

Combination and Sequential 2

Static Combinational Network CMOS Circuits VDD • Pull-up network-PMOS • Pull-down network- NMOS • Networks are complementary to each other • When the circuit is dormant, no current flows between supply lines. • Number of the NMOS transistors (PMOS transistors) equals to the number of the inputs. • Output load is capacitive PMOS Network Output Inputs NMOS Network 3

NAND Gates Transistors in Parallel 1/Rcheff = (1/Rch 1) + (1/Rch 2) Transistors in Series Rcheff = Rch 1 + Rch 2 4

CMOS NAND Gate DC Analysis Two possible scenarios: 1. Both inputs are toggling 2. One input is toggling, the other one set high Assumptions: MP 2=MP 1=MP MN 1=MN 2=MN W/L for MP = (W/L)p W/L for MN = (W/L)n Inverter VTC 5

Gate Sizing To obtain equal Rise and Fall time, Size the series / parallel transistors to have an equivalent of a single PU or PD inverter transistor in your design 6

Sizing the CMOS Gate 7

NAND Gates: Analysis Scenario #1 Both inputs are toggling L-H > (W/L)eff = 2(W/L)p H-L > (W/L)eff = 1/2(W/L)n KR|NAND = 1/4 KR|INV Vin Inverter V OH Scenario #2 One input is toggling L-H > (W/L)eff = (W/L)p H-L > (W/L)eff = 1/2(W/L)n KR|NAND = 1/2 KR|INV One input toggling Two inputs toggling Vin=Vout VOL Vx 2 Vx 1 Vout 8

NAND Gate: Power Dissipation Pac= α. f. C VDD 2 A B 0 0 1 1 1 X 1 1 1 0 α = P (X=1). P (X=0) assuming A and B have equal probabilities for 1 and 0 α = (1/4). (3/4)= 3/16 C = CL + C parasitic 10

Increasing the inputs 11

NOR Gate: Analysis DC Analysis/ AC Analysis Two possible scenarios: 1. Both inputs are toggling (one is set low) 2. One input is toggling, the other one set high Assumptions: AP 2=BP 1=MP AN 1=BN 2=MN W/L for MP = (W/L)p W/L for MN = (W/L)n Compare with a CMOS inverter: MP/MN KR, and the shift in VTC Propagation delay t. PLH and t. PHL 12

4 INPUT NOR Gate VDD A Very slow rise time and rise delays B Could be compensated by increasing of PMOS transistor size. C Implications: Silicon Area Input capacitance D X A B C D CL 13

Practical Considerations 1. Minimize the use of NOR gates 2. Minimize the fan-in of NOR gates 3. Limit the fan-in to 4 for NAND gates 4. Use De morgan’s theorem to reduce the number of fan -in per gate Example: 14

Complex CMOS Gate 15

Reducing Output Capacitance 16

Pseudo n. MOS 17

Pseudo n. MOS NAND/NOR Gates From Lecture #4 For acceptable operation WN=1. 5 WP for our Process respecting min WP 18

Pseudo n. MOS Complex Gates From Lecture #4 For acceptable operation WN=1. 5 WP for our Process respecting min WP 19

CASCODE LOGIC Lad is cross coupled p. MOS transistors Logic is series and parallel complementary transistors Input and Output are in Complementary forms 20

CSACODE Inverter/Nand Gate 21

CASCODE Complex Gate 22

DCVS trees for a full adder Sum and Carry Pull. Down Networks S’(A, B, C) = A’BC’ + A’B’C + AB’C’ S (A, B, C) = A’B’C’ + A’BC + ABC’ + AB’C C(A, B, C) = AB + BC + AC 23

Transmission Gate Bi-directional switch, passes digital signals Less complex and more versatile than AND gate Passes analog signals C A Problems: Large ON resistance during transitions of input signals Large input and output capacitance (useful for data storage applications) Capacitive coupling B C Applications: Multiplexers, encoders, latches, registers various combinational logic circuits 24

NMOS/PMOS as Pass Transistors NMOS Transistor C Vo Passes weak “ 1” signal Vo = VDD -VTN Passes “ 0” signal undegraded VDD -VTN Vi Vo CL VDD -VTN Vi PMOS Transistor Vo C Passes “ 1” signal undegraded Passes weak “ 0” signal Vo= -VTP Vi -VTP Vo CL -VTP Vi 25

TX Gate: Characteristics Vo Vin nmos: lin nmos: sat pmos: lin 0 V |VTP| nmos: off pmos: lin VDD-VTN VDD 0 26

AND, NAND A B F 0 0 1 1 1 27

OR, NOR A B F 0 0 1 1 1 0 1 1 28

A multiplexer C A B F 0 0 1 0 0 0 1 1 1 0 0 1 1 0 1 1 1 1 29

XOR A B F 0 0 1 1 1 0 30

Four to one multiplexer 31

TX Gate: Layout C P+ VDD P+ Vi VO N+ N+ C VSS C C For data path structure 32

NAND Gates: Layout Transistors in Series Transistors in Parallel 33

NAND Gates: Layout VDD Via Metal II X A B GND 34

NOR Gate: Layout VDD X B A GND 35

Analysis and Design of Complex Gate Analysis p+ layer A B C D E F VDD 1. Construct the schematic 2. Determine the logic function. 3. Determine transistor sizes. 4. Determine the input pattern to cause slowest and fastest operations. 5. Determine the worst case rise delay (t. PLH)and fall delay (t. PHL) 6. Determine the best case rise and fall delays. OUT contact N-well GND n+ layer A B polysilicon C D E metal F active (diffusion) 36