CMOS Analog Design Using AllRegion MOSFET Modeling Chapter

CMOS Analog Design Using All-Region MOSFET Modeling Chapter 11 MOSFET parameter extraction for design CMOS Analog Design Using All-Region MOSFET Modeling

Specific current and threshold voltage For VDS/ t<<1 we have if ir or For VDS/ t=1/2 and if=3, we have IS ID. For VDS/ t=1/2 and if=3, more accurate values for gm/ID and IS are 0. 53 times the peak value of gm/ID and 1. 13 times the measured current, respectively. CMOS Analog Design Using All-Region MOSFET Modeling 2

Transconductance-to-current ratio of a MOSFET vs. gate voltage for VDS Φt/2 and VS=0. CMOS Analog Design Using All-Region MOSFET Modeling 3

Pinch-off voltage vs. gate voltage For if=3, the pinch-off voltage is equal to the source voltage. CMOS Analog Design Using All-Region MOSFET Modeling 4

Slope factor n=1/(d. VP/d. VG) vs. gate voltage CMOS Analog Design Using All-Region MOSFET Modeling 5

Plot of 1/(n-1)2 vs. pinch-off voltage The slope and the y-intercept of the interpolation line give =0. 60 V 1/2 and 2 F=0. 89 V CMOS Analog Design Using All-Region MOSFET Modeling 6

Mobility - 1 The dependence of the mobility on the transverse electric field is written as Problem: Determine the mobility variation for cases in which the depletion charge is much higher than the inversion charge density with CMOS Analog Design Using All-Region MOSFET Modeling 7

Mobility-2 VG + VS+ t/2 VS Parameter VT 0 2 F Value 0. 89 V 0. 60 V 1/2 8. 8 A 0. 75 V-1/2 0. 552 V CMOS Analog Design Using All-Region MOSFET Modeling 8

Comparison between experiment and the ACM model in a 0. 35 m technology-1 Experiment and ACM model for a long-channel (L=3. 2 m) NMOS transistor in a 0. 35 m CMOS technology, with VS=0 and VDS= 13 m. V. The maximum error for currents is around 30% for VG = 3. 3 V CMOS Analog Design Using All-Region MOSFET Modeling 9

Comparison between experiment and the ACM model in a 0. 35 m technology-2 Plots of experimental and modeled transconductance-to-current ratio vs. drain current CMOS Analog Design Using All-Region MOSFET Modeling 10

Comparison between experiment and the ACM model in a 0. 35 m technology-3 Plot of the experimental and modeled current vs. gate voltage for a minimum-length NMOS transistor in a 0. 35 m technology. CMOS Analog Design Using All-Region MOSFET Modeling 11

The Early voltage -1 CMOS Analog Design Using All-Region MOSFET Modeling 12

The Early voltage -2 Experimental drain and source currents versus drain-to-source voltage for a minimum channel length NMOS transistor (L=0. 4 m) in a 0. 35 m CMOS technology. CMOS Analog Design Using All-Region MOSFET Modeling 13

The Early voltage -3 Derivatives of the experimental drain and source currents with respect to the drain voltage versus drain-to-source voltage for a minimum channel length NMOS transistor (L=0. 4 m) in a 0. 35 m CMOS technology. CMOS Analog Design Using All-Region MOSFET Modeling 14

The Early voltage -4 Experimental and modeled Early voltages vs. drain-to-source voltage for a minimum-length NMOS transistor (L=0. 4 m) in a 0. 35 m CMOS technology CMOS Analog Design Using All-Region MOSFET Modeling 15

The Early voltage - 5 Experimental and modeled Early voltages vs. drain-to-source voltage for transistors M 1, M 2, M 4, and M 8, for which the nominal lengths are Lmin, 2·Lmin, 4·Lmin, 8·Lmin, respectively, where Lmin=0. 4 m. CMOS Analog Design Using All-Region MOSFET Modeling 16

The Early voltage - 6 Fitting parameters extracted for the Early voltage of NMOS transistors in a 0. 35 m CMOS technology. Transistor [m. V/V] a [V/m 2] M 1 7 2. 5 1014 0. 1 M 2 0. 8 2. 5 1014 0. 1 M 4 0. 6 2. 5 1014 0. 1 M 8 0. 45 2. 5 1014 0. 1 [V] CMOS Analog Design Using All-Region MOSFET Modeling 17