CLOCKLESS CHIPS Submitted by Abi Mathew Roll No

CLOCKLESS CHIPS Submitted by Abi Mathew Roll No: 1

CONTENTS 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. INTRODUCTION BASIC CONCEPT OF CLOCK WORKING OF SYNCHRONIZE CHIPS ADVANTAGES & DISADVANTAGES WORKING OF ASYNCHRONOUS CHIPS ADVANTAGES AND DISADVANTAGES TYPES OF ASYNCHRONOUS DESIGN COMPARISON APPLICATIONS OF CLOCKLESS CHIPS BRIEF HISTORY CONCLUSION

INTODUCTION Ø Ø CLOCKLESS CHIPS OR ASYNCHRONOUS CHIPS DON’T HAVE A GLOBAL CLOCK. BUT THERE SHOULD BE SOME CONTROL MECHANISM INSTEAD OF GLOBAL CLOCKED CHIPS OR SYNCHRONOUS CHIPS HAVE A GLOBAL CLOCK FOR CONTROLLING TIMING OF ENTIRE CHIP. CLOCKLESS CHIPS HAVE SOME ADVANTAGES LIKE LOW POWER CONSUMPTION, HIGH SPEED & LESS ELECTROMAGNETIC NOISE OVER CLOCKED CHIP.

CONCEPT OF CLOCK Clock is a tiny crystal oscillator. Clock regulates the rate at which the instructions are executed. This rate is known as clock rate or clock speed. The clock speed can be expressed in terms of gigahertz and megahertz. One advantage of clock is that the clock signals to various components inside a chip when to input and output can be determined very easy. Because of this clock there are some disadvantages like high power consumption, low speed which can be overcome by clockless chips.

BLOCK DIAGRAM OF SYNCHRONOUS CIRCUIT

SYNCHRONOUS CHIPS ADVANTAGE Ø CHIP DESIGN VERY SIMPLE BECAUSE OF CLOCK DISADVANTAGES Ø WASTAGE OF COMPUTATIONAL TIME AFFECTS THE SPEED OF CHIP Ø HIGHER POWER CONSUMPTION Ø DESIGN OF COMPLEX CIRCUITS CANNOT BE DONE BECAUSE OF HIGH POWER CONSUMPTION

BLOCK DIAGRAM OF ASYNCHRONOUS CHIPS

MERITS OF ASYNCHRONOUS CIRCUITS ü ü ü ü Increase in speed. Reduced power consumption. Less electromagnetic noise. The ability to provide superior encryption. It is very flexible. Replacing any part with a faster version improves the speed again and again Designers have more freedom in choosing the system’s part.

LIMITATIONS OF ASYNCHRONOUS CIRCUITS Design difficulties. n Lack of good tools. n Testing difficulties. n

TYPES OF IMPLEMENTATIONS n n n BOUNDED DELAY METHOD DELAY INSENSITIVE METHOD NULL CONVENTIONAL LOGIC(NCL)

SPEED COMPARISON

POWER COMPARISON

A BRIEF HISTORY

COMPANY ACHIEVEMENTS GOALS SUN MICROSYSTEMS Palo Alto, CA Prototypes have demonstrated two to three times the speed of Standard chips. Gradually integrate “islands” of clockless logic into future Generations of microprocessors. INTEL Santa Clara, CA Clockless prototype Stay current with in 1997 ran three clockless R&D. times faster than the conventional chip equivalent, on half the power. ASYNCHRONOUS DIGITAL DESIGN Pasadena, CA Founded by students of Caltech’s Alain Martin, who developed the First asynchronous microprocessor. Produce chips for cell phones and other low-power communications devices; expected to announce plans by Year-end.

THESEUS LOGIC Patented “null Maitland, FL convention logic, ” a way of letting clockless chips know when an operation is Complete. License designs to manufacturers of smart cards and mobile devices; Motorola is a current customer. PHILIPS ELECTRONICS Eindhoven, Netherlands Markets a clockless chip that gives its pagers up to twice the battery life of competitors. Clockless chips for mobile devices and smart cards. SELF-TIMED SOLUTIONS Manchester, England Founded Steve Furber who has developed clockless chips for communications devices. Clockless chips for smart cards.

The Caltech Asynchronous Microprocessor is the world’s first asynchronous microprocessor (1989).

APPLICATIONS v MOBILE ELECTRONICS v PERSONAL COMPUTERS v ENCRYPTION DEVICES

CONCLUSION Clocks are getting faster, while chips are getting bigger, both of which make clock distribution harder. Chips are also becoming more heterogeneous, with functions like memory and network interfaces being considered, all of which complicates the global timing analysis necessary for a synchronous design. Finally, we are entering an age when processors will be just about everywhere, and this will require very low power designs. It’s just not practical to expect a clean, skew-free clock for every (say) piece of clothing with a processing element. But this can only happen if more focus, especially at the university level, is given to asynchronous design. Most of today’s designers don’t understand it well enough to use it, and may even regard it with suspicion. It is certainly a challenge, but just as the software community is moving towards more concurrency, the hardware community must move to incorporate asynchronous logic.

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