CLICpix test setup status Pierpaolo Valerio Clic Pix

CLICpix test setup status Pierpaolo Valerio

Clic. Pix daughter board n n n Components for the board were selected, ordered and (finally) received. A schematic of the board has been drawn and verified Layout is currently being made (with help from Jerome Alozy) The design should be finished by this week, so that the board can be produced by next week The board mainly consists of: q q Level translator for logic (high speed) differential signals Voltage regulators for chip powering (tuneable for further testing) Trimmers to provide global biasing to the chip Connectors and test points

Clic. Pix testing firmware n n The FPGA test board used for the readout has been tested The firmware is in a preliminary stage (I can send and receive data, macros to perform standard operations need to be programmed) but it has been validated The available FPGA is powerful enough to complete a full-frame readout without the need of a PC (storing the frame in internal registers). Communication speed could not be tested without the daughter board (but according to the specifications >320 Mbps rates are achievable).

Nest steps n n The daughter board should be ready in two weeks The die needs to be wire bonded to the board. The CERN bonding lab is already aware of the work to be done I expect first functional tests to start shortly after Help will be needed with more complex testing routines (to validate the performances of the chip in a more “realistic” environment!