CLICpix 2 and C 3 PD Bump Pads

CLICpix 2 and C 3 PD Bump Pads E. Santin, P. Valerio, I. Kremastiotis & R. Ballabriga Sune CLICdp Vertex Meeting CERN, February 12 th 2016

Motivation n Define the bump pads layout for the C 3 PD chip (based on the CLICpix 2 bump pads) n Summarize (and get feedback of, if any) the final bump pads layouts for both chips: CLICpix 2 & C 3 PD 2

Topological cross-section of 1 st prototype Cpx = undesirable caps crosstalks Cp 1 Cp 3 Cp 4 C 3 PD bump pad Ctotal CLICpix 1 bump pad n Cp 2 via Aim: Maximize Ctotal and minimize Cpx 3

An approximate study… TSMC 65 nm cross-section AP Ctotal M 6 ASSUMPTIONS AP layer of TSMC 65 nm as the CLICpix 2 bump pad Assume M 6 of TSMC 65 nm as the C 3 PD bump pad some limitations wrt the actual scenario: • Different dielectric height • Different dielectric material • Different (M 6 -approximated) C 3 PD pad thickness “absolute” values shown next do not match the reality 4

Accurate 3 D field solver layout Calibre x. ACT 3 D Extracted parasitics 5

Coupling capacitances without GRs 15µm 3, 1 C 2, 2 TOP 3, 2 CLICpix 2 2, 1 C 2, 2 BOT 3, 3 C 2, 2 BOTto. TOP C 2, 2 BOTto 2, 1 BOT C 2, 2 BOTto 2, 3 BOT C 2, 2 BOTto. OTHERS =11. 5 f. F = 0. 14 f. F = 0. 12 f. F < 0. 07 f. F C 3 PD 2, 2 2, 3 create signal crosstalks we want to minimize this phenomenon 1, 1 n 1, 2 1, 3 Without guard rings (GRs), there are capacitive couplings from C 2, 2 BOT (i. e. C 3 PD bump pad) to all other bump pads (i. e. adjacent C 3 PD and CLICpix 2 pads). The couplings to the CLICpix 2 pads are, however, very small. 6

Coupling capacitances with GRs 15µm 3, 1 3, 2 3, 3 2, 2 2, 3 4µm 1, 1 n 1, 2 =11. 2 f. F = 2. 5 f. F not a problem 2µm 2, 1 C 2, 2 BOTto. TOP C 2, 2 BOTto. VSSA 1, 3 ea r a ngs n to i r rd tio rable a u l u o G s si e d d o go ze un s! i lk a m t i s n s mi cro With guard rings (GRs) around the C 3 PD bump pads, the capacitive coupling from C 2, 2 BOT to other adjacent bump pads are negligible. On the other hand, there is a fixed capacitance between the pads and the analog ground, Vssa, which is not a problem. 7

Final CLICpix 2 bump pads layout bump pad 12µm 14µm 25µm 8µm via 6µm 22. 5µm 10µm n n Bump pad size is 240 µm 2 Vias adjacent to the bump pad openings to comply with foundry DRC rules 8

Final C 3 PD bump pads layout bump pad 2µm 15µm 25µm 15µm 4µm guard ring n n Bump pad size is about 15 x 15 µm 2 Guard rings around the bump pads are connected to the same low-noise, low-impedance voltage (i. e. Vssa) and they minimize inter-pad (capacitive) coupling 9

Conclusion n CLICpix 2 bump pad final size is imposed by the power distribution grid and technology constraints (i. e. via) C 3 PD bump pad final size is imposed by the “shielding” guard rings (to minimize crosstalks) Open question: Is it possible to avoid the passivation layer on the C 3 PD chip to increase Ctotal (i. e. the intended coupling capacitance between C 3 PD and CLICpix 2 bump pads)? 10

Thank you for your attention!

Backup slides

Capacitance between two plates Ctotal = Carea + Cfringe http: //maxwell. ucdavis. edu/~electro/dc_circuits/images/cap_fields. jpg n Total capacitance is a result of two components: area capacitance, Carea, and fringe capacitance, Cfringe n Question: Which one of the two dominates in the CLICpix 2 and C 3 PD bump pads arrangement? 13

Extracted coupling capacitances (using TSMC 65 nm back-end layers as an approximation) CLICpix 2 bump pad vs three C 3 PD bump pad layouts Case 1 Ctotal=15. 1 f. F n Case 2 Case 3 Ctotal=10. 7 f. F (-29%) Ctotal=16. 3 f. F (+8%) Case 2 should favor the fringe capacitance component, but since the Ctotal is smaller than the other two cases it tells us that the area capacitance component dominates in these three scenarios q But, do not ignore the analysis limitations mentioned on slide 4 14