Classification of instructions 4 address instructions 3 address

Classification of instructions • • • 4 -address instructions 3 -address instructions 2 -address instructions 1 -address instructions 0 -address instructions 1

CS 501 Advanced Computer Architecture Lecture 02 Dr. Noor Muhammad Sheikh 2

Advanced Computer Architecture 3

Foundation of Computer Architecture 4

Taxonomy of Computer 5

Classes of SA 6

Instruction Set Features 7

Classification of instructions (continued…) • The 4 -address instruction specifies the two source operands, the destination operand the address of the next instruction op code destination source 1 source 2 next address 8

Classification of instructions (continued…) • A 3 -address instruction specifies addresses for both operands as well as the result op code destination source 1 source 2 9

Classification of instructions (continued…) • A 2 -address instruction overwrites one operand with the result • One field serves two purposes op code destination source 1 source 2 • A 1 -address instruction has a dedicated CPU register, called the accumulator, to hold one operand & the result –No address is needed to specify the accumulator op code source 2 10

Classification of instructions (continued…) • A 0 -address instruction uses a stack to hold both operands and the result. Operations are performed between the value on the top of the stack TOS) and the second value on the stack (SOS) and the result is stored on the TOS op code 11

Comparison of instruction formats As an example assume: • that a single byte is used for the op code • the size of the memory address space is 16 Mbytes • a single addressable memory unit is a byte • Size of operands is 24 bits • Data bus size is 8 bits 12

Comparison of instruction formats (continued…) • We will use the following two parameters to compare the five instruction formats mentioned before • Code size § Has an effect on the storage requirements • Number of memory accesses § Has an effect on execution time 13

4 -address instruction op code destination source 1 source 2 next address 1 byte 3 bytes • Code size = 1+3+3 = 13 bytes • No of bytes accessed from memory 13 bytes for instruction fetch + 6 bytes for source operand fetch + 3 bytes for storing destination operand Total = 22 bytes 14

3 -address instruction op code destination source 1 source 2 1 byte 3 bytes • Code size = 1+3+3+3 = 10 bytes • No of bytes accessed from memory 10 bytes for instruction fetch + 6 bytes for source operand fetch + 3 bytes for storing destination operand Total = 19 bytes 15

2 -address instruction op code destination source 1 source 2 1 byte 3 bytes • Code size = 1+3+3 = 7 bytes • No of bytes accessed from memory 7 bytes for instruction fetch + 6 bytes for source operand fetch + 3 bytes for storing destination operand Total = 16 bytes 16

1 -address instruction op code source 2 1 byte 3 bytes • Code size = 1+3= 4 bytes • No of bytes accessed from memory 4 bytes for instruction fetch + 3 bytes for source operand fetch + 0 bytes for storing destination operand Total = 7 bytes 17

0 -address instruction op code 1 byte • Code size = 1= 1 bytes • # of bytes accessed from memory 1 bytes for instruction fetch + 6 bytes for source operand fetch + 3 bytes for storing destination operand Total = 10 bytes 18

Summary 19

Example 2. 1 text expression evaluation a = (b+c)*d - e 20

Immediate Addressing Mode • Data for the instruction is part of the instruction itself • No need to calculate any address • Limited range of operands: for n bit fields, -2^(n-1) to +(2^(n-1)-1) 21

Immediate addressing mode Example: lda 123 *** IR Op code 123 : Memory : data ACC 123 No memory access needed *** Note we have used the lda instruction: as an example to maintain consistency and: to limit the number of operands to one only 22

Direct Addressing mode Example: lda [123] *** IR Opcode Memory 123 address ACC 456 123 data . . . *** Other asm notations or formats may be used 23

Indirect addressing mode Example: lda [[123]] IR Opcode Memory 123 Address of pointer 456 Address of data ACC 789 data 123 : 789 456 24

Register (direct) addressing mode (continued…) Example: lda R 2 IR Op code : Memory : address of R 2 Address of data R 1 R 2 1234 R 3 R 4 ACC data : : 1234 No memory access needed 25

Register Indirect Addressing Example: lda [R 1] IR Op code Address of R 1 the instruction points to a CPU register R 1 R 2 R 3 R 4 123 CPU Registers ACC Memory register contains memory address 456 123 data 456 26

Displacement Addressing constant Example: lda [ R 1 + 8 ] Op code Address of R 1 8 ress d d a ster + Regi R 1 R 2 Index 456 128 120 CPU registers ACC Memory address data IR Memory 456 27

Relative Addressing Example: jump 4 Memory IR Opcode 4 + 120 Next instruction 124 …. . . PC Address of the next instruction 28

RISC • Stands for Reduced Instruction Set Computers • A concept or philosophy of machine design; not a set of architectural features • Underlying idea is to reduce the number and complexity of instructions • New RISC computers may have some instruction that are quite complex 29

Features of RISC machines • One instruction per clock period • All instructions have the same size • CPU accesses memory only for Load and Store operations • Simple and few addressing modes 30

CISC Complex Instruction Set Computers 31

Features of CISC machines • More work per instruction • Wide variety of addressing modes • Variable instruction lengths and execution times per instruction • CISC machines attempt to reduce the “semantic gap” 32

Disadvantages of CISC • Clock period, T, cannot be reduced beyond a certain limit • Complex addressing modes delay operand fetch from memory • Difficult to make efficient use of speedup techniques 33