Checker Mode A Hybrid Scheme for Timing Analysis

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Checker. Mode : A Hybrid Scheme for Timing Analysis of Modern Processor Pipelines involving

Checker. Mode : A Hybrid Scheme for Timing Analysis of Modern Processor Pipelines involving Hardware/Software Interactions Ø Sibin Ø Ø Mohan and Frank Mueller ( [email protected] ncsu. edu, [email protected] ncsu. edu ) Computer Science Department, North Carolina State University

Motivation Ø Modern processor features make static analysis difficult l Out of order execution

Motivation Ø Modern processor features make static analysis difficult l Out of order execution l Branch prediction, etc. Ø Dynamic timing analysis l Does not guarantee safety of results Ø Hence, real-time designers l Forced to avoid contemporary processors and features Ø Hybrid approach to timing analysis obtain WCET l Takes advantage of interactions between hardware/software Ø We propose minor additions to micro-architecture of processor pipelines l To aid in the process of obtaining accurate WCET of tasks 3/12/2021 Sibin Mohan : RTAS 2007 WIP, April 2007 2

Checker. Mode Overview Constant interactions between hardware/software Ø Task code split into feasible execution

Checker. Mode Overview Constant interactions between hardware/software Ø Task code split into feasible execution paths Ø Conditional execution Ø l All alternate paths are timed separately on processor Checkpoint/snapshot of processor state is captured Ø Instruction Semantics Ø l Input-dependent values may not be available l We associate a Not-A-Number (Na. N) l Semantics of instruction must be modified to handle this: 3/12/2021 Sibin Mohan : RTAS 2007 WIP, April 2007 3

Framework Tuning Knob Path PCs Path Exec Time Driver Path 1 exec time Path

Framework Tuning Knob Path PCs Path Exec Time Driver Path 1 exec time Path 2 exec time Reg BP Snapshot Pipeline Curr PC Start/Stop PC I$ D$ Exec Cycles Checker. Mode Path n exec time Timing Analyzer Snapshot Manager Thursday, August 03, 2006 Software Side 4 Hardware Side

Results Ø 1 Three configurations of Simple. Scalar Processor simulator l Sim-IO, Superscalar-IO, Out-of-Order

Results Ø 1 Three configurations of Simple. Scalar Processor simulator l Sim-IO, Superscalar-IO, Out-of-Order Ø Execution time measurement techniques: L 2 l Short, Path-Aggregate, Program-Aggregate Friday, March 12, 2021 3 R 4 5

Conclusion Hybrid mechanism for timing analysis Ø Checker. Mode processors Ø l Drive execution

Conclusion Hybrid mechanism for timing analysis Ø Checker. Mode processors Ø l Drive execution along program paths l Capture/write back processor state (“snapshots”). Ø Contemporary processors predictable and analyzable l Available for use in real-time systems Thanks ! Ø Questions? Ø 3/12/2021 Sibin Mohan : RTAS 2007 WIP, April 2007 6

Backup Slides 3/12/2021 Sibin Mohan : RTAS 2007 WIP, April 2007 7

Backup Slides 3/12/2021 Sibin Mohan : RTAS 2007 WIP, April 2007 7

Checker. Mode Operation Path p 1 Reg Snapshot IF Exec time(p 1) = e

Checker. Mode Operation Path p 1 Reg Snapshot IF Exec time(p 1) = e 1 BP ID Snapshot s 1 branch Issue Q EX EX EX Exec time(p 2) = e 2 WB D$ Path p 2 Path p 3 IR I$ Pipeline Exec time(p 3) = e 3 Merge Path p 4 Merged State Exec time = p 8 merge

Path composition Results Composition without overlap with overlap Fixed point

Path composition Results Composition without overlap with overlap Fixed point